Scatter store non-temporal bytes
Scatter store non-temporal of bytes from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory.
A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 2 classes: 32-bit unscaled offset and 64-bit unscaled offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | Rm | 0 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 8;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 8;
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(VL) base; bits(64) offset; bits(VL) src; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = TRUE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, esize) then base = Z[n, VL]; offset = X[m, 64]; src = Z[t, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(64) baddr = ZeroExtend(Elem[base, e, esize], 64); constant bits(64) addr = AddressAdd(baddr, offset, accdesc); Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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