STP

Store Pair of Registers calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about addressing modes, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Signed offset

Post-index

313029282726252423222120191817161514131211109876543210
x010100010imm7Rt2RnRt
opcVRL

32-bit (opc == 00)

STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>

64-bit (opc == 10)

STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>

boolean wback = TRUE; boolean postindex = TRUE;

Pre-index

313029282726252423222120191817161514131211109876543210
x010100110imm7Rt2RnRt
opcVRL

32-bit (opc == 00)

STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!

64-bit (opc == 10)

STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!

boolean wback = TRUE; boolean postindex = FALSE;

Signed offset

313029282726252423222120191817161514131211109876543210
x010100100imm7Rt2RnRt
opcVRL

32-bit (opc == 00)

STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]

64-bit (opc == 10)

STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]

boolean wback = FALSE; boolean postindex = FALSE;

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly STP.

Assembler Symbols

<Wt1>

Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Wt2>

Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

For the 32-bit post-index and 32-bit pre-index variant: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.

For the 64-bit post-index and 64-bit pre-index variant: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.

For the 32-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.

For the 64-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

<Xt1>

Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xt2>

Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); if L:opc<0> == '01' || opc == '11' then UNDEFINED; integer scale = 2 + UInt(opc<1>); constant integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale); boolean tagchecked = wback || n != 31; boolean rt_unknown = FALSE; if wback && (t == n || t2 == n) && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is pre-writeback when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

Operation

bits(64) address; bits(64) address2; bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); if rt_unknown && t == n then data1 = bits(datasize) UNKNOWN; else data1 = X[t, datasize]; if rt_unknown && t2 == n then data2 = bits(datasize) UNKNOWN; else data2 = X[t2, datasize]; if IsFeatureImplemented(FEAT_LSE2) then bits(2*datasize) full_data; if BigEndian(accdesc.acctype) then full_data = data1:data2; else full_data = data2:data1; accdesc.ispair = TRUE; Mem[address, 2*dbytes, accdesc] = full_data; else address2 = AddressIncrement(address, dbytes, accdesc); Mem[address, dbytes, accdesc] = data1; Mem[address2, dbytes, accdesc] = data2; if wback then if postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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