SUBPS

Subtract Pointer, setting Flags subtracts the 56-bit address held in the second source register from the 56-bit address held in the first source register, sign-extends the result to 64-bits, and writes the result to the destination register. It updates the condition flags based on the result of the subtraction.

This instruction is used by the alias CMPP.

Integer
(FEAT_MTE)

313029282726252423222120191817161514131211109876543210
10111010110Xm000000XnXd
sfSopcode

SUBPS <Xd>, <Xn|SP>, <Xm|SP>

if !IsFeatureImplemented(FEAT_MTE) then UNDEFINED; integer d = UInt(Xd); integer n = UInt(Xn); integer m = UInt(Xm);

Assembler Symbols

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Xd" field.

<Xn|SP>

Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Xn" field.

<Xm|SP>

Is the 64-bit name of the second general-purpose source register or stack pointer, encoded in the "Xm" field.

Alias Conditions

AliasIs preferred when
CMPPS == '1' && Xd == '11111'

Operation

bits(64) operand1 = if n == 31 then SP[] else X[n, 64]; bits(64) operand2 = if m == 31 then SP[] else X[m, 64]; operand1 = SignExtend(operand1<55:0>, 64); operand2 = NOT(SignExtend(operand2<55:0>, 64)); bits(64) result; bits(4) nzcv; (result, nzcv) = AddWithCarry(operand1, operand2, '1'); X[d, 64] = result; PSTATE.<N,Z,C,V> = nzcv;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.