SWP, SWPA, SWPAL, SWPL -- A64

Swap word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register.

Integer
(FEAT_LSE)

if !IsFeatureImplemented(FEAT_LSE) then UNDEFINED; integer s = UInt(Rs); integer t = UInt(Rt); integer n = UInt(Rn); constant integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; boolean acquire = A == '1' && Rt != '11111'; boolean release = R == '1'; boolean tagchecked = n != 31;

Assembler Symbols

<Ws>	Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Wt>	Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xs>	Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Xt>	Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

Operation

bits(64) address; bits(datasize) data; bits(datasize) store_value; AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; store_value = X[s, datasize]; bits(datasize) comparevalue = bits(datasize) UNKNOWN; // Irrelevant when not executing CAS data = MemAtomic(address, comparevalue, store_value, accdesc); X[t, regsize] = ZeroExtend(data, regsize);

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	x	1	1	1	0	0	0	A	R	1	Rs					1	0	0	0	0	0	Rn					Rt
size					VR											o3	opc