This instruction starts a new transaction. If the transaction started successfully, the destination register is set to zero. If the transaction failed or was canceled, then all state modifications that were performed transactionally are discarded and the destination register is written with a nonzero value that encodes the cause of the failure.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Rt | ||||
| op1 | CRn | CRm | op2 | ||||||||||||||||||||||||||||
TSTART <Xt>
if !IsFeatureImplemented(FEAT_TME) then UNDEFINED; integer t = UInt(Rt);
if !IsTMEEnabled() then UNDEFINED; boolean IsEL1Regime; bit tme; bit tmt; case PSTATE.EL of when EL0 IsEL1Regime = S1TranslationRegime() == EL1; if IsEL1Regime then tme = SCTLR_EL1.TME0; tmt = SCTLR_EL1.TMT0; else tme = SCTLR_EL2.TME0; tmt = SCTLR_EL2.TMT0; when EL1 tme = SCTLR_EL1.TME; tmt = SCTLR_EL1.TMT; when EL2 tme = SCTLR_EL2.TME; tmt = SCTLR_EL2.TMT; when EL3 tme = SCTLR_EL3.TME; tmt = SCTLR_EL3.TMT; otherwise Unreachable(); boolean enable = tme == '1'; boolean trivial = tmt == '1'; if !enable then TransactionStartTrap(t); elsif trivial then TSTATE.nPC = NextInstrAddr(64); TSTATE.Rt = t; FailTransaction(TMFailure_TRIVIAL, FALSE); elsif IsFeatureImplemented(FEAT_SME) && PSTATE.SM == '1' then FailTransaction(TMFailure_ERR, FALSE); elsif TSTATE.depth == 255 then FailTransaction(TMFailure_NEST, FALSE); elsif TSTATE.depth == 0 then TSTATE.nPC = NextInstrAddr(64); TSTATE.Rt = t; ClearExclusiveLocal(ProcessorID()); TakeTransactionCheckpoint(); StartTrackingTransactionalReadsWrites(); TSTATE.depth = TSTATE.depth + 1; X[t, 64] = Zeros(64);
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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