Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
The UADDW instruction extracts vector elements from the lower half of the second source register. The UADDW2 instruction extracts vector elements from the upper half of the second source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | size | 1 | Rm | 0 | 0 | 0 | 1 | 0 | 0 | Rn | Rd | |||||||||||||
U | o1 |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; boolean sub_op = (o1 == '1'); boolean unsigned = (U == '1');
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Ta> |
Is an arrangement specifier,
encoded in
|
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
<Tb> |
Is an arrangement specifier,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n, 2*datasize]; bits(datasize) operand2 = Vpart[m, part, datasize]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d, 2*datasize] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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