UDOT (4-way, multiple and indexed vector)

Multi-vector unsigned integer dot-product by indexed element

The unsigned integer dot product instruction computes the dot product of four unsigned 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the two or four first source vectors and four unsigned 8-bit or 16-bit integer values in the corresponding indexed 32-bit or 64-bit element of the second source vector. The widened dot product result is destructively added to the corresponding 32-bit or 64-bit element of the ZA single-vector groups.

The groups within the second source vector are specified using an immediate element index which selects the same group position within each 128-bit vector segment. The index range is from 0 to one less than the number of groups per 128-bit segment, encoded in 1 to 2 bits depending on the size of the group.

The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.

It has encodings from 4 classes: Two ZA single-vectors of 32-bit elements , Two ZA single-vectors of 64-bit elements , Four ZA single-vectors of 32-bit elements and Four ZA single-vectors of 64-bit elements

Two ZA single-vectors of 32-bit elements
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 32; constant integer n = UInt(Zn:'0'); constant integer m = UInt('0':Zm); constant integer offset = UInt(off3); constant integer index = UInt(i2); constant integer nreg = 2;

Two ZA single-vectors of 64-bit elements
(FEAT_SME_I16I64)

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 64; constant integer n = UInt(Zn:'0'); constant integer m = UInt('0':Zm); constant integer offset = UInt(off3); constant integer index = UInt(i1); constant integer nreg = 2;

Four ZA single-vectors of 32-bit elements
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 32; constant integer n = UInt(Zn:'00'); constant integer m = UInt('0':Zm); constant integer offset = UInt(off3); constant integer index = UInt(i2); constant integer nreg = 4;

Four ZA single-vectors of 64-bit elements
(FEAT_SME_I16I64)

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 64; constant integer n = UInt(Zn:'00'); constant integer m = UInt('0':Zm); constant integer offset = UInt(off3); constant integer index = UInt(i1); constant integer nreg = 4;