UMINP

Compute the minimum value of each pair of adjacent unsigned integer elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer m = UInt(Zm); constant integer dn = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>	Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(VL) result; integer element1; integer element2; for e = 0 to elements-1 if !ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = Elem[operand1, e, esize]; else if IsEven(e) then element1 = UInt(Elem[operand1, e + 0, esize]); element2 = UInt(Elem[operand1, e + 1, esize]); else element1 = UInt(Elem[operand2, e - 1, esize]); element2 = UInt(Elem[operand2, e + 0, esize]); constant integer res = Min(element1, element2); Elem[result, e, esize] = res<esize-1:0>; Z[dn, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
- The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:

The MOVPRFX must be unpredicated.
The MOVPRFX must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	0	size		0	1	0	1	1	1	1	0	1	Pg			Zm					Zdn
															U

UMINP

UMINP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Assembler Symbols

Operation

Operational information