UQDECP (scalar)

Unsigned saturating decrement scalar by count of true predicate elements

Counts the number of true elements in the source predicate and then uses the result to decrement the scalar destination. The result is saturated to the general-purpose register's unsigned integer range.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit

313029282726252423222120191817161514131211109876543210
00100101size1010111000100PmRdn
DUsf

UQDECP <Wdn>, <Pm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer m = UInt(Pm); constant integer dn = UInt(Rdn); constant boolean unsigned = TRUE; constant integer ssize = 32;

64-bit

313029282726252423222120191817161514131211109876543210
00100101size1010111000110PmRdn
DUsf

UQDECP <Xdn>, <Pm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer m = UInt(Pm); constant integer dn = UInt(Rdn); constant boolean unsigned = TRUE; constant integer ssize = 64;

Assembler Symbols

<Wdn>

Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Xdn>

Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Pm>

Is the name of the source scalable predicate register, encoded in the "Pm" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(ssize) operand1 = X[dn, ssize]; constant bits(PL) operand2 = P[m, PL]; bits(ssize) result; integer count = 0; for e = 0 to elements-1 if ActivePredicateElement(operand2, e, esize) then count = count + 1; constant integer element = Int(operand1, unsigned); (result, -) = SatQ(element - count, ssize, unsigned); X[dn, 64] = Extend(result, 64, unsigned);

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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