Multi-vector unsigned saturating rounding shift right narrow by immediate
Shift right by an immediate value, the unsigned integer value in each element of the four source vectors and place the rounded results in the quarter-width destination elements. Each result element is saturated to the quarter-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per source element.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | tsize | 1 | imm5 | 1 | 1 | 0 | 1 | 1 | 0 | Zn | 0 | 1 | Zd | |||||||||||
| N | U | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if tsize == '00' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd); constant integer shift = (8 * esize) - UInt(tsize:imm5);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
| <const> |
Is the immediate shift amount, in the range 1 to number of bits per source element, encoded in "tsize:imm5". |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (4 * esize); bits(VL) result; for r = 0 to 3 constant bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 constant bits(4 * esize) element = Elem[operand, e, 4 * esize]; constant integer res = (UInt(element) + (1 << (shift-1))) >> shift; Elem[result, r*elements + e, esize] = UnsignedSat(res, esize); Z[d, VL] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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