UQRSHRN

Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave

Shift right by an immediate value, the unsigned integer value in each element of the four source vectors and place the four-way interleaved rounded results in the quarter-width destination elements. Each result element is saturated to the quarter-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per source element.

This instruction is unpredicated.

SME2
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001tsize1imm5110111Zn01Zd
NU

UQRSHRN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const>

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if tsize == '00' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd); constant integer shift = (8 * esize) - UInt(tsize:imm5);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tsize:

tsize <T>
00 RESERVED
01 B
1x H
<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Tb>

Is the size specifier, encoded in tsize:

tsize <Tb>
00 RESERVED
01 S
1x D
<Zn4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

<const>

Is the immediate shift amount, in the range 1 to number of bits per source element, encoded in "tsize:imm5".

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (4 * esize); bits(VL) result; for e = 0 to elements-1 for i = 0 to 3 constant bits(VL) operand = Z[n+i, VL]; constant bits(4 * esize) element = Elem[operand, e, 4 * esize]; constant integer res = (UInt(element) + (1 << (shift-1))) >> shift; Elem[result, 4*e + i, esize] = UnsignedSat(res, esize); Z[d, VL] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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