UZP1, UZP2 (predicates)

Concatenate even or odd elements from two predicates

Concatenate adjacent even or odd-numbered elements from the first and second source predicates and place in elements of the destination predicate. This instruction is unpredicated.

It has encodings from 2 classes: Even and Odd

Even

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100100Pn0Pd
H

UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Pn); constant integer m = UInt(Pm); constant integer d = UInt(Pd); constant integer part = 0;

Odd

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100110Pn0Pd
H

UZP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Pn); constant integer m = UInt(Pm); constant integer d = UInt(Pd); constant integer part = 1;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Pn>

Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm>

Is the name of the second source scalable predicate register, encoded in the "Pm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer pairs = VL DIV (esize * 2); constant bits(PL) operand1 = P[n, PL]; constant bits(PL) operand2 = P[m, PL]; bits(PL) result; for p = 0 to pairs - 1 Elem[result, p, esize DIV 8] = Elem[operand1, 2*p+part, esize DIV 8]; for p = 0 to pairs - 1 Elem[result, pairs+p, esize DIV 8] = Elem[operand2, 2*p+part, esize DIV 8]; P[d, PL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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