WHILEGT (predicate as counter)

Generate a predicate for a group of two or four vectors that starting from the highest numbered element of the group is true while the decrementing value of the first, signed scalar operand is greater than the second scalar operand and false thereafter down to the lowest numbered element of the group.

The full width of the scalar operands is significant for the purposes of comparison, and the full width first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size.

The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

SVE2
(FEAT_SVE2p1)

if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer rsize = 64; constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer d = UInt('1':PNd); constant boolean unsigned = FALSE; constant boolean invert = TRUE; constant SVECmp op = Cmp_GT; constant integer width = 2 << UInt(vl);

Assembler Symbols

<PNd>

Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<Xn>	Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field.

<Xm>	Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field.

<vl>

Is the vl specifier, encoded in vl:

vl	<vl>
0	VLx2
1	VLx4

Operation

if IsFeatureImplemented(FEAT_SVE2p1) then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = width * (VL DIV esize); bits(rsize) operand1 = X[n, rsize]; constant bits(rsize) operand2 = X[m, rsize]; bits(PL) result; boolean last = TRUE; integer count = 0; for e = elements-1 downto 0 boolean cond; case op of when Cmp_GT cond = (Int(operand1, unsigned) > Int(operand2, unsigned)); when Cmp_GE cond = (Int(operand1, unsigned) >= Int(operand2, unsigned)); last = last && cond; if last then count = count + 1; operand1 = operand1 - 1; result = EncodePredCount(esize, elements, count, invert, PL); PSTATE.<N,Z,C,V> = PredCountTest(elements, count, invert); P[d, PL] = result;

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	1	size		1	Rm					0	1	vl	0	0	0	Rn					1	1	PNd
																				U	lt							eq