Interleave elements from four vectors
Place the four-way interleaved elements from the four source vectors in the corresponding elements of the four destination vectors.
This instruction is unpredicated.
It has encodings from 2 classes: 8-bit to 64-bit elements and 128-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 0 | 0 | |||||
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if size == '11' && MaxImplementedSVL() < 256 then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00');
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 0 | 0 | ||||
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if MaxImplementedSVL() < 512 then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00');
| <Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4. |
| <T> |
Is the size specifier,
encoded in
|
| <Zd4> |
Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. |
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 4 then UNDEFINED; constant integer quads = VL DIV (esize * 4); constant bits(VL) operand0 = Z[n, VL]; constant bits(VL) operand1 = Z[n+1, VL]; constant bits(VL) operand2 = Z[n+2, VL]; constant bits(VL) operand3 = Z[n+3, VL]; bits(VL) result; for r = 0 to 3 constant integer base = r * quads; for q = 0 to quads-1 Elem[result, 4*q+0, esize] = Elem[operand0, base+q, esize]; Elem[result, 4*q+1, esize] = Elem[operand1, base+q, esize]; Elem[result, 4*q+2, esize] = Elem[operand2, base+q, esize]; Elem[result, 4*q+3, esize] = Elem[operand3, base+q, esize]; Z[d+r, VL] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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