The CNTPCT characteristics are:
Holds the 64-bit physical count value.
AArch32 System register CNTPCT bits [63:0] are architecturally mapped to AArch64 System register CNTPCT_EL0[63:0].
This register is present only when AArch32 is supported. Otherwise, direct accesses to CNTPCT are UNDEFINED.
All reads to the CNTPCT occur in program order relative to reads to CNTPCTSS or CNTPCT.
CNTPCT is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Physical count value | |||||||||||||||||||||||||||||||
| Physical count value | |||||||||||||||||||||||||||||||
Physical count value.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
| coproc | CRm | opc1 |
|---|---|---|
| 0b1111 | 0b1110 | 0b0000 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PCTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else AArch64.AArch32SystemAccessTrap(EL1, 0x04); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PCTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PCTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PCTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCTEN == '0' then AArch32.TakeHypTrapException(0x04); else if IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && !ELUsingAArch32(EL2) && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' && !ELIsInHost(EL0) then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTPOFF_EL2, 32); else (R[t2], R[t]) = Split(PhysicalCountInt(), 32); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && CNTHCTL_EL2.EL1PCTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCTEN == '0' then AArch32.TakeHypTrapException(0x04); else if IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && !ELUsingAArch32(EL2) && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTPOFF_EL2, 32); else (R[t2], R[t]) = Split(PhysicalCountInt(), 32); elsif PSTATE.EL == EL2 then (R[t2], R[t]) = Split(PhysicalCountInt(), 32); elsif PSTATE.EL == EL3 then (R[t2], R[t]) = Split(PhysicalCountInt(), 32);
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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