CPSR

This register is present only when AArch32 is supported. Otherwise, direct accesses to CPSR are UNDEFINED.

Attributes

Field descriptions

N, bit [31]

Negative condition flag. Set to bit[31] of the result of the last flag-setting instruction. If the result is regarded as a two's complement signed integer, then N is set to 1 if the result was negative, and N is set to 0 if the result was positive or zero.

Z, bit [30]

Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0 otherwise. A result of zero often indicates an equal result from a comparison.

C, bit [29]

Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for example an unsigned overflow on an addition.

V, bit [28]

Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition, for example a signed overflow on an addition.

Q, bit [27]

Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions.

Bits [26:24]

SSBS, bit [23]
When FEAT_SSBS is implemented:

Speculative Store Bypass Safe.

Prohibits speculative loads or stores that might practically allow a cache timing side channel.

A cache timing side channel might be exploited where a load or store uses an address that is derived from a register that is being loaded from memory using a load instruction speculatively read from a memory location. If PSTATE.SSBS is enabled, the address derived from the load instruction might be from earlier in the coherence order than the latest store to that memory location with the same virtual address.

SSBS	Meaning
0b0	Hardware is not permitted to load or store speculatively in the manner described.
0b1	Hardware is permitted to load or store speculatively in the manner described.

The value of this bit is usually set to the value described by the SCTLR.DSSBS bit on exceptions to any mode except Hyp mode, and the value described by HSCTLR.DSSBS on exceptions to Hyp mode.

The reset behavior of this field is:

On a Warm reset, this field resets to an IMPLEMENTATION DEFINED value.

Otherwise:

PAN, bit [22]
When FEAT_PAN is implemented:

Privileged Access Never.

PAN	Meaning
0b0	The translation system is the same as Armv8.0.
0b1	Disables privileged read and write accesses to addresses accessible at EL0.

The value of this bit is usually preserved on taking an exception, except in the following situations:

When the target of the exception is EL1, and the value of the SCTLR.SPAN bit for the current Security state is 0, this bit is set to 1.
When the target of the exception is EL3, from Secure state, and the value of the Secure SCTLR.SPAN is 0, this bit is set to 1.
When the target of the exception is EL3, from Non-secure state, this bit is set to 0 regardless of the value of the Secure SCTLR.SPAN bit.

Otherwise:

DIT, bit [21]
When FEAT_DIT is implemented:

Data Independent Timing.

DIT	Meaning
0b0	The architecture makes no statement about the timing properties of any instructions.
0b1	The architecture requires that: The timing of every load and store instruction is insensitive to the value of the data being loaded or stored. For certain data processing instructions, the instruction takes a time that is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. For certain data processing instructions, the response of the instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags.

DIT

Meaning

0b0

The architecture makes no statement about the timing properties of any instructions.

0b1

The architecture requires that:

The timing of every load and store instruction is insensitive to the value of the data being loaded or stored.
For certain data processing instructions, the instruction takes a time that is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
For certain data processing instructions, the response of the instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

The Operational Information section of a data processing instruction description indicates if that instruction is affected by this bit.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Otherwise:

Bit [20]

GE, bits [19:16]

Greater than or Equal flags, for parallel addition and subtraction.

Bits [15:10]

E, bit [9]

Endianness state bit. Controls the load and store endianness for data accesses:

E	Meaning
0b0	Little-endian operation
0b1	Big-endian operation.

Instruction fetches ignore this bit.

If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.

If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.

Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.

When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.

A, bit [8]

SError exception mask bit.

A	Meaning
0b0	Exception not masked.
0b1	Exception masked.

I, bit [7]

IRQ mask bit.

I	Meaning
0b0	Exception not masked.
0b1	Exception masked.

F, bit [6]

FIQ mask bit.

F	Meaning
0b0	Exception not masked.
0b1	Exception masked.

Bit [5]

Bit [4]

M, bits [3:0]

Current PE mode.

M	Meaning
0b0000	User.
0b0001	FIQ.
0b0010	IRQ.
0b0011	Supervisor.
0b0110	Monitor.
0b0111	Abort.
0b1010	Hyp.
0b1011	Undefined.
0b1111	System.

CPSR, Current Program Status Register

Purpose

Configuration

Attributes

Field descriptions

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Q, bit [27]

Bits [26:24]

SSBS, bit [23]
When FEAT_SSBS is implemented:

Otherwise:

PAN, bit [22]
When FEAT_PAN is implemented:

Otherwise:

DIT, bit [21]
When FEAT_DIT is implemented:

Otherwise:

Bit [20]

GE, bits [19:16]

Bits [15:10]

E, bit [9]

A, bit [8]

I, bit [7]

F, bit [6]

Bit [5]

Bit [4]

M, bits [3:0]

Accessing CPSR

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
N	Z	C	V	Q	RES0			SSBS	PAN	DIT	RES0	GE				RES0						E	A	I	F	RES0	RES1	M

CPSR, Current Program Status Register

Purpose

Configuration

Attributes

Field descriptions

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Q, bit [27]

Bits [26:24]

SSBS, bit [23]When FEAT_SSBS is implemented:

Otherwise:

PAN, bit [22]When FEAT_PAN is implemented:

Otherwise:

DIT, bit [21]When FEAT_DIT is implemented:

Otherwise:

Bit [20]

GE, bits [19:16]

Bits [15:10]

E, bit [9]

A, bit [8]

I, bit [7]

F, bit [6]

Bit [5]

Bit [4]

M, bits [3:0]

Accessing CPSR

SSBS, bit [23]
When FEAT_SSBS is implemented:

PAN, bit [22]
When FEAT_PAN is implemented:

DIT, bit [21]
When FEAT_DIT is implemented: