The ID_ISAR5 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR4.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_ISAR5 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR5_EL1[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_ISAR5 are UNDEFINED.
ID_ISAR5 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VCMA | RDM | RES0 | CRC32 | SHA2 | SHA1 | AES | SEVL | ||||||||||||||||||||||||
Indicates AArch32 support for complex number addition and multiplication where numbers are stored in vectors.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| VCMA | Meaning |
|---|---|
| 0b0000 |
The VCMLA and VCADD instructions are not implemented in AArch32. |
| 0b0001 |
The VCMLA and VCADD instructions are implemented in AArch32. |
All other values are reserved.
FEAT_FCMA implements the functionality identified by 0b0001.
From Armv8.3, the value 0b0000 is not permitted.
Access to this field is RO.
Indicates support for the VQRDMLAH and VQRDMLSH instructions in AArch32 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| RDM | Meaning |
|---|---|
| 0b0000 |
No VQRDMLAH and VQRDMLSH instructions implemented. |
| 0b0001 |
VQRDMLAH and VQRDMLSH instructions implemented. |
All other values are reserved.
FEAT_RDM implements the functionality identified by the value 0b0001.
From Armv8.1, the value 0b0000 is not permitted.
Access to this field is RO.
Reserved, RES0.
Indicates support for the CRC32 instructions CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW in AArch32 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CRC32 | Meaning |
|---|---|
| 0b0000 |
CRC32 instructions are not implemented. |
| 0b0001 |
The specified instructions are implemented. |
All other values are reserved.
FEAT_CRC32 implements the functionality identified by the value 0b0001.
From Armv8.1, the value 0b0000 is not permitted.
Access to this field is RO.
Indicates support for the SHA2 instructions SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 in AArch32 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SHA2 | Meaning |
|---|---|
| 0b0000 |
No SHA2 instructions implemented. |
| 0b0001 |
The specified instructions are implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
Access to this field is RO.
Indicates support for the SHA1 instructions SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 in AArch32 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SHA1 | Meaning |
|---|---|
| 0b0000 |
No SHA1 instructions implemented. |
| 0b0001 |
The specified instructions are implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
Access to this field is RO.
Indicates support for the AES instructions in AArch32 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| AES | Meaning |
|---|---|
| 0b0000 |
No AES instructions implemented. |
| 0b0001 |
AESE, AESD, AESMC, and AESIMC implemented. |
| 0b0010 |
As for 0b0001, plus VMULL (polynomial) instructions operating on 64-bit data quantities. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0010.
Access to this field is RO.
Indicates support for the SEVL instruction in AArch32 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SEVL | Meaning |
|---|---|
| 0b0000 |
SEVL is implemented as a NOP. |
| 0b0001 |
SEVL is implemented as Send Event Local. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0010 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else R[t] = ID_ISAR5; elsif PSTATE.EL == EL2 then R[t] = ID_ISAR5; elsif PSTATE.EL == EL3 then R[t] = ID_ISAR5;
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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