The ID_MMFR2 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_MMFR2 bits [31:0] are architecturally mapped to AArch64 System register ID_MMFR2_EL1[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_MMFR2 are UNDEFINED.
ID_MMFR2 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HWAccFlg | WFIStall | MemBarr | UniTLB | HvdTLB | L1HvdRng | L1HvdBG | L1HvdFG | ||||||||||||||||||||||||
Hardware Access Flag. In earlier versions of the Arm Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HWAccFlg | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Support for VMSAv7 Access flag, updated in hardware. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| WFIStall | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Support for WFI stalling. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
Access to this field is RO.
Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc == 1111) encoding space.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MemBarr | Meaning |
|---|---|
| 0b0000 |
None supported. |
| 0b0001 | Supported memory barrier System instructions are:
|
| 0b0010 | As for 0b0001, and adds:
|
All other values are reserved.
In Armv8-A, the only permitted value is 0b0010.
Arm deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions.
Access to this field is RO.
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| UniTLB | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 | Supported unified TLB maintenance operations are:
|
| 0b0010 | As for 0b0001, and adds:
|
| 0b0011 | As for 0b0010, and adds:
|
| 0b0100 | As for 0b0011, and adds:
|
| 0b0101 |
As for 0b0100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL,TLBIMVALH. |
| 0b0110 |
As for 0b0101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0110.
Access to this field is RO.
If the value of ID_MMFR2.UniTLB is not 0b0000, then the meaning of this field is IMPLEMENTATION DEFINED. Arm deprecates the use of this field by software.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| L1HvdRng | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 | Supported Level 1 Harvard cache maintenance range operations are:
|
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| L1HvdBG | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 | Supported Level 1 Harvard cache background fetch operations are:
|
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| L1HvdFG | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 | Supported Level 1 Harvard cache foreground fetch operations are:
|
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0001 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else R[t] = ID_MMFR2; elsif PSTATE.EL == EL2 then R[t] = ID_MMFR2; elsif PSTATE.EL == EL3 then R[t] = ID_MMFR2;
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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