JIDR

This register is present only when AArch32 is supported. Otherwise, direct accesses to JIDR are UNDEFINED.

Attributes

Field descriptions

Bits [31:0]

Accessing JIDR

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1110	0b111	0b0000	0b0000	0b000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JIDR UNDEFINED at EL0" then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL0) && HCR_EL2.TID0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID0 == '1' then AArch32.TakeHypTrapException(0x05); else R[t] = JIDR; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID0 == '1' then AArch32.TakeHypTrapException(0x05); else R[t] = JIDR; elsif PSTATE.EL == EL2 then R[t] = JIDR; elsif PSTATE.EL == EL3 then R[t] = JIDR;

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RAZ

JIDR, Jazelle ID Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:0]

Accessing JIDR

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}