JMCR

This register is present only when AArch32 is supported. Otherwise, direct accesses to JMCR are UNDEFINED.

Attributes

Field descriptions

Bits [31:0]

Accessing JMCR

For accesses from EL0 it is IMPLEMENTATION DEFINED whether the register is RW or UNDEFINED.

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1110	0b111	0b0010	0b0000	0b000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JMCR UNDEFINED at EL0" then UNDEFINED; else R[t] = JMCR; elsif PSTATE.EL == EL1 then R[t] = JMCR; elsif PSTATE.EL == EL2 then R[t] = JMCR; elsif PSTATE.EL == EL3 then R[t] = JMCR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1110	0b111	0b0010	0b0000	0b000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JMCR UNDEFINED at EL0" then UNDEFINED; else return; elsif PSTATE.EL == EL1 then return; elsif PSTATE.EL == EL2 then return; elsif PSTATE.EL == EL3 then return;

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RAZ/WI

JMCR, Jazelle Main Configuration Register