VDISR

AArch32 System register VDISR bits [31:0] are architecturally mapped to AArch64 System register VDISR_EL2[31:0].

This register is present only when EL1 is capable of using AArch32 and FEAT_RAS is implemented. Otherwise, direct accesses to VDISR are UNDEFINED.

If EL2 is not implemented, then VDISR is RES0 from Monitor mode when SCR.NS == 1.

Attributes

Field descriptions

When TTBCR.EAE == 0:

A, bit [31]

Bits [30:16]

AET, bits [15:14]

Bit [13]

ExT, bit [12]

Bit [11]

FS, bits [10, 3:0]

LPAE, bit [9]

Bits [8:4]

When TTBCR.EAE == 1:

A, bit [31]

Bits [30:16]

AET, bits [15:14]

Bit [13]

ExT, bit [12]

Bits [11:10]

LPAE, bit [9]

Bits [8:6]

STATUS, bits [5:0]

FS	Meaning
0b10110	Asynchronous SError exception.

LPAE	Meaning
0b0	Using the Short-descriptor translation table format.

LPAE	Meaning
0b1	Using the Long-descriptor translation table format.

STATUS	Meaning
0b010001	Asynchronous SError exception.

Accessing VDISR

Direct reads and writes of VDFSR are UNDEFINED if EL3 is implemented and using AArch32 in all Secure privileged modes other than Monitor mode.

An indirect write to VDISR made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR occurring in program order after the ESB instruction.

If EL2 is not implemented, then VDISR is RES0 from Monitor mode when SCR.NS == 1.

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b100	0b1100	0b0001	0b001

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b100	0b1100	0b0001	0b001

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1100	0b0001	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2.TMEA == '1')) then R[t] = VDISR_EL2<31:0>; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.AMO == '1' then R[t] = VDISR; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3.EA == '1' then R[t] = Zeros(32); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && !Halted() && SCR.EA == '1' then R[t] = Zeros(32); else R[t] = DISR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3.EA == '1' then R[t] = Zeros(32); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && !Halted() && SCR.EA == '1' then R[t] = Zeros(32); else R[t] = DISR; elsif PSTATE.EL == EL3 then R[t] = DISR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1100	0b0001	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2.TMEA == '1')) then VDISR_EL2 = R[t]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.AMO == '1' then VDISR = R[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3.EA == '1' then return; elsif HaveEL(EL3) && ELUsingAArch32(EL3) && !Halted() && SCR.EA == '1' then return; else DISR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3.EA == '1' then return; elsif HaveEL(EL3) && ELUsingAArch32(EL3) && !Halted() && SCR.EA == '1' then return; else DISR = R[t]; elsif PSTATE.EL == EL3 then DISR = R[t];

VDISR, Virtual Deferred Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

When TTBCR.EAE == 0:

A, bit [31]

Bits [30:16]

AET, bits [15:14]

Bit [13]

ExT, bit [12]

Bit [11]

FS, bits [10, 3:0]

LPAE, bit [9]

Bits [8:4]

When TTBCR.EAE == 1:

A, bit [31]

Bits [30:16]

AET, bits [15:14]

Bit [13]

ExT, bit [12]

Bits [11:10]

LPAE, bit [9]

Bits [8:6]

STATUS, bits [5:0]

Accessing VDISR

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
A	RES0															AET		RES0	ExT	RES0	FS[4]	LPAE	RES0					FS[3:0]