AMEVCNTVOFF0<n>_EL2, Activity Monitors Event Counter Virtual Offset Registers 0, n = 0 - 15

The AMEVCNTVOFF0<n>_EL2 characteristics are:

Purpose

Holds the 64-bit virtual offset for architected activity monitor events.

Configuration

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMEVCNTVOFF0<n>_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

AMEVCNTVOFF0<n>_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Virtual offset
Virtual offset

Bits [63:0]

Virtual offset.

The reset behavior of this field is:

Accessing AMEVCNTVOFF0<n>_EL2

If <n> is not 0, 2 or 3, reads and writes of AMEVCNTVOFF0<n>_EL2 are UNDEFINED.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AMEVCNTVOFF0<m>_EL2 ; Where m = 0-15

op0op1CRnCRmop2
0b110b1000b11010b100:m[3]m[2:0]

integer m = UInt(CRm<0>:op2<2:0>); if m >= 4 then UNDEFINED; elsif !(m IN {0, 2, 3}) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0xA00 + (8 * m)]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.AMVOFFEN == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.AMVOFFEN == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMEVCNTVOFF0_EL2[m]; elsif PSTATE.EL == EL3 then X[t, 64] = AMEVCNTVOFF0_EL2[m];

MSR AMEVCNTVOFF0<m>_EL2, <Xt> ; Where m = 0-15

op0op1CRnCRmop2
0b110b1000b11010b100:m[3]m[2:0]

integer m = UInt(CRm<0>:op2<2:0>); if m >= 4 then UNDEFINED; elsif !(m IN {0, 2, 3}) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0xA00 + (8 * m)] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.AMVOFFEN == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.AMVOFFEN == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else AMEVCNTVOFF0_EL2[m] = X[t, 64]; elsif PSTATE.EL == EL3 then AMEVCNTVOFF0_EL2[m] = X[t, 64];


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.