CNTP_TVAL

AArch64 System register CNTP_TVAL_EL0 bits [31:0] are architecturally mapped to AArch32 System register CNTP_TVAL[31:0].

Attributes

Field descriptions

Bits [63:32]

TimerValue, bits [31:0]

The TimerValue view of the EL1 physical timer.

On a read of this register:

If CNTP_CTL_EL0.ENABLE is 0, the value returned is UNKNOWN.
If CNTP_CTL_EL0.ENABLE is 1, the value returned is (CNTP_CVAL_EL0 - CNTPCT_EL0).

On a write of this register, CNTP_CVAL_EL0 is set to (CNTPCT_EL0 + TimerValue), where TimerValue is treated as a signed 32-bit integer.

When CNTP_CTL_EL0.ENABLE is 1, the timer condition is met when (CNTPCT_EL0 - CNTP_CVAL_EL0) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:

CNTP_CTL_EL0.ISTATUS is set to 1.
If CNTP_CTL_EL0.IMASK is 0, an interrupt is generated.

When CNTP_CTL_EL0.ENABLE is 0, the TimerValue cannot be read but continues to decrement. When the timer is enabled, the TimerValue represents the elapsed time whether that time was spent enabled or disabled.

Note

The value of CNTPCT_EL0 used in these calculations is the value seen at the Exception level that the CNTPCT_EL0 register is being read or written from.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing CNTP_TVAL_EL0

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name CNTP_TVAL_EL0 or CNTP_TVAL_EL02 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CNTP_TVAL_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0010	0b000

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then if CNTHPS_CTL_EL2.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTHPS_CVAL_EL2 - PhysicalCountInt(); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then if CNTHP_CTL_EL2.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTHP_CVAL_EL2 - PhysicalCountInt(); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' && !ELIsInHost(EL0) then if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - (PhysicalCountInt() - CNTPOFF_EL2); else if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - PhysicalCountInt(); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - (PhysicalCountInt() - CNTPOFF_EL2); else if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - PhysicalCountInt(); elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then if CNTHPS_CTL_EL2.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTHPS_CVAL_EL2 - PhysicalCountInt(); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then if CNTHP_CTL_EL2.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTHP_CVAL_EL2 - PhysicalCountInt(); else if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - PhysicalCountInt(); elsif PSTATE.EL == EL3 then if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - PhysicalCountInt();

MSR CNTP_TVAL_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0010	0b000

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' && !ELIsInHost(EL0) then CNTP_CVAL_EL0 = (SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt()) - CNTPOFF_EL2; else CNTP_CVAL_EL0 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then CNTP_CVAL_EL0 = (SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt()) - CNTPOFF_EL2; else CNTP_CVAL_EL0 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); else CNTP_CVAL_EL0 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); elsif PSTATE.EL == EL3 then CNTP_CVAL_EL0 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt();

MRS <Xt>, CNTP_TVAL_EL02

op0	op1	CRn	CRm	op2
0b11	0b101	0b1110	0b0010	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - PhysicalCountInt(); else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then if CNTP_CTL_EL0.ENABLE == '0' then X[t, 64] = bits(64) UNKNOWN; else X[t, 64] = CNTP_CVAL_EL0 - PhysicalCountInt(); else UNDEFINED;

MSR CNTP_TVAL_EL02, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b101	0b1110	0b0010	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then CNTP_CVAL_EL0 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then CNTP_CVAL_EL0 = SignExtend(X[t, 64]<31:0>, 64) + PhysicalCountInt(); else UNDEFINED;

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RES0
TimerValue

CNTP_TVAL_EL0, Counter-timer Physical Timer TimerValue Register

Purpose

Configuration