DC GZVA, Data Cache set Allocation Tags and Zero by VA

Executing DC GZVA

When this instruction is executed, it can generate memory faults or watchpoints which are prioritized in the same way as other memory-related faults or watchpoints. If a synchronous Data Abort fault or a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is not set.

If the memory region being zeroed is any type of Device memory, this instruction generates an alignment fault which is prioritized in the same way as other alignment faults that are determined by the memory type.

This instruction applies to Normal memory regardless of cacheability attributes.

This instruction behaves as a set of Stores to each byte and Allocation tag within the block being accessed, and so it:

• Generates a Permission fault if the translation system does not permit writes to the locations.
• Requires the same considerations for ordering and the management of coherency as any other store instructions.

Accesses to this instruction use the following encodings in the System instruction encoding space:

op0	op1	CRn	CRm	op2
0b01	0b011	0b0111	0b0100	0b100

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1.DZE == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2.TDZ == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCZVA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.DZE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.MemZero(X[t, 64], CacheType_Data_Tag); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TDZ == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCZVA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.MemZero(X[t, 64], CacheType_Data_Tag); elsif PSTATE.EL == EL2 then AArch64.MemZero(X[t, 64], CacheType_Data_Tag); elsif PSTATE.EL == EL3 then AArch64.MemZero(X[t, 64], CacheType_Data_Tag);