ICC_BPR0

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption.

Configuration

AArch64 System register ICC_BPR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ICC_BPR0[31:0].

This register is present only when GICv3 is implemented. Otherwise, direct accesses to ICC_BPR0_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:3]

BinaryPoint, bits [2:0]

The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:

Binary point value	Group priority field	Subpriority field	Field with binary point
0	[7:1]	[0]	ggggggg.s
1	[7:2]	[1:0]	gggggg.ss
2	[7:3]	[2:0]	ggggg.sss
3	[7:4]	[3:0]	gggg.ssss
4	[7:5]	[4:0]	ggg.sssss
5	[7:6]	[5:0]	gg.ssssss
6	[7]	[6:0]	g.sssssss
7	No preemption	[7:0]	.ssssssss

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing ICC_BPR0_EL1

The minimum binary point value is derived from the number of implemented priority bits. The number of priority bits is IMPLEMENTATION DEFINED, and reported by:

ICC_CTLR_EL1.PRIbits
ICC_CTLR_EL3.PRIbits An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value.

On a reset, the binary point field is UNKNOWN.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_BPR0_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1100	0b1000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FIQ == '1' then UNDEFINED; elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2.TALL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FMO == '1' then X[t, 64] = ICV_BPR0_EL1; elsif HaveEL(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ICC_BPR0_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FIQ == '1' then UNDEFINED; elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ICC_BPR0_EL1; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ICC_BPR0_EL1;

MSR ICC_BPR0_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1100	0b1000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FIQ == '1' then UNDEFINED; elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2.TALL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FMO == '1' then ICV_BPR0_EL1 = X[t, 64]; elsif HaveEL(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else ICC_BPR0_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FIQ == '1' then UNDEFINED; elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else ICC_BPR0_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else ICC_BPR0_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																													BinaryPoint

ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0

Purpose