ID_AA64FPFR0

Provides information about the FP8 formats and instructions implemented in AArch64 state.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

Attributes

Field descriptions

Bits [63:32]

F8CVT, bit [31]

Indicates support for the following instructions:

The Advanced SIMD floating-point scaling instruction FSCALE.
The Advanced SIMD FP8 convert instructions BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2, F1CVTL, F1CVTL2, F2CVTL, F2CVTL2, FCVTN, and FCVTN2.
When FEAT_SVE2 or FEAT_SME2 is implemented, the SVE2 FP8 convert instructions BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT, F1CVT, F1CVTLT, F2CVT, F2CVTLT, BFCVTN, FCVTN, FCVTNB, and FCVTNT.
When FEAT_SME2 is implemented, the SME2 multi-vector floating-point scaling instruction FSCALE and the SME2 FP8 convert instructions BF1CVT, BF1CVTL, BF2CVT, BF2CVTL, F1CVT, F1CVTL, F2CVT, F2CVTL, BFCVT, FCVT, and FCVTN.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F8CVT	Meaning
0b0	The specified instructions are not implemented.
0b1	The specified instructions are implemented.

FEAT_FP8 implements the functionality identified by the value 1.

Access to this field is RO.

F8FMA, bit [30]

Indicates support for the following instructions:

The Advanced SIMD FP8 to single-precision and half-precision multiply-accumulate instructions FMLALB, FMLALT, FMLALLBB, FMLALLBT, FMLALLTB, and FMLALLTT.
When FEAT_SVE2 is implemented and the PE is not in Streaming SVE mode, the SVE2 FP8 to single-precision and half-precision multiply-accumulate instructions FMLALB, FMLALT, FMLALLBB, FMLALLBT, FMLALLTB, and FMLALLTT.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F8FMA	Meaning
0b0	The specified instructions are not implemented.
0b1	The specified instructions are implemented.

FEAT_FP8FMA implements the functionality identified by the value 1.

Access to this field is RO.

F8DP4, bit [29]

Indicates support for the following instructions:

Advanced SIMD FP8 to single-precision 4-way dot product FDOT (4-way) instructions.
When FEAT_SVE2 is implemented and the PE is not in Streaming SVE mode, SVE2 FP8 to single-precision 4-way dot product FDOT (4-way) instructions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F8DP4	Meaning
0b0	The specified instructions are not implemented by this feature.
0b1	The specified instructions are implemented.

Note

Other features may implement some of the specified instructions.

All other values are reserved.

FEAT_FP8DOT4 implements the functionality identified by the value 1.

Access to this field is RO.

F8DP2, bit [28]

Indicates support for the following instructions:

Advanced SIMD FP8 to half-precision 2-way dot product FDOT (2-way) instructions.
When FEAT_SVE2 is implemented and the PE is not in Streaming SVE mode, SVE2 FP8 to half-precision 2-way dot product FDOT (2-way) instructions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F8DP2	Meaning
0b0	The specified instructions are not implemented by this feature.
0b1	The specified instructions are implemented.

Note

Other features may implement some of the specified instructions.

FEAT_FP8DOT2 implements the functionality identified by the value 1.

Access to this field is RO.

Bits [27:2]

F8E4M3, bit [1]

Indicates support for Arm FP8 E4M3 format and behavior for FP8 instructions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F8E4M3	Meaning
0b0	Arm FP8 E4M3 format is not supported.
0b1	Arm FP8 E4M3 format is supported.

If FEAT_FP8 is implemented, the only permitted value is 1.

Otherwise, the only permitted value is 0.

Access to this field is RO.

F8E5M2, bit [0]

Indicates support for Arm FP8 E5M2 format and behavior for FP8 instructions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F8E5M2	Meaning
0b0	Arm FP8 E5M2 format is not supported.
0b1	Arm FP8 E5M2 format is supported.

If FEAT_FP8 is implemented, the only permitted value is 1.

Otherwise, the only permitted value is 0.

Access to this field is RO.

Accessing ID_AA64FPFR0_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_AA64FPFR0_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0000	0b0100	0b111

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64FPFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64FPFR0_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64FPFR0_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64FPFR0_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64FPFR0_EL1;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
F8CVT	F8FMA	F8DP4	F8DP2	RES0																										F8E4M3	F8E5M2

ID_AA64FPFR0_EL1, AArch64 Floating-point Feature Register 0

Purpose

Configuration

Attributes

Field descriptions

Bits [63:32]

F8CVT, bit [31]

F8FMA, bit [30]

F8DP4, bit [29]

F8DP2, bit [28]

Bits [27:2]

F8E4M3, bit [1]

F8E5M2, bit [0]

Accessing ID_AA64FPFR0_EL1

MRS <Xt>, ID_AA64FPFR0_EL1