The MECIDR_EL2 characteristics are:
MEC identification register.
This register is present only when FEAT_MEC is implemented. Otherwise, direct accesses to MECIDR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
MECIDR_EL2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | MECIDWidthm1 |
Reserved, RES0.
MECID width minus 1.
The value of this field plus 1 is the MECID width in bits, that this PE supports.
MECIDWidthm1 | Meaning |
---|---|
0b0000..0b1111 |
The number of bits of MECID supported by the PE, minus 1. |
The value 0b1111 indicates that this PE supports a MECID width of 16 bits, and provides 216 possible MECID values.
MECIDWidth is defined as MECIDR_EL2.MECIDWidthm1 + 1.
For accesses from EL2 and EL3, this register is RO.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1010 | 0b1000 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = MECIDR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = MECIDR_EL2;
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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