The MIDR_EL1 characteristics are:
Provides identification information for the PE, including an implementer code for the device and a device ID number.
AArch64 System register MIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MIDR[31:0].
AArch64 System register MIDR_EL1 bits [31:0] are architecturally mapped to External register MIDR_EL1[31:0].
MIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| Implementer | Variant | Architecture | PartNum | Revision | |||||||||||||||||||||||||||
Reserved, RES0.
The Implementer code. This field must hold an implementer code that has been assigned by Arm.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Implementer | Meaning |
|---|---|
| 0x00 |
Reserved for software use. |
| 0x41 |
Arm Limited. |
| 0x42 |
Broadcom Corporation. |
| 0x43 |
Cavium Inc. |
| 0x44 |
Digital Equipment Corporation. |
| 0x46 |
Fujitsu Ltd. |
| 0x49 |
Infineon Technologies AG. |
| 0x4D |
Motorola or Freescale Semiconductor Inc. |
| 0x4E |
NVIDIA Corporation. |
| 0x50 |
Applied Micro Circuits Corporation. |
| 0x51 |
Qualcomm Inc. |
| 0x56 |
Marvell International Ltd. |
| 0x69 |
Intel Corporation. |
| 0xC0 |
Ampere Computing. |
Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.
Access to this field is RO.
Variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Architecture version.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Architecture | Meaning |
|---|---|
| 0b0001 |
Armv4. |
| 0b0010 |
Armv4T. |
| 0b0011 |
Armv5 (obsolete). |
| 0b0100 |
Armv5T. |
| 0b0101 |
Armv5TE. |
| 0b0110 |
Armv5TEJ. |
| 0b0111 |
Armv6. |
| 0b1111 |
Architectural features are individually identified in the ID_* registers. |
All other values are reserved.
Access to this field is RO.
Primary Part Number for the device.
On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Revision number for the device.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.MIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() then X[t, 64] = VPIDR_EL2; else X[t, 64] = MIDR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = MIDR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MIDR_EL1;
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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