PAN

This register is present only when FEAT_PAN is implemented. Otherwise, direct accesses to PAN are UNDEFINED.

Attributes

Field descriptions

Bits [63:23]

PAN, bit [22]

Privileged Access Never.

PAN	Meaning
0b0	Privileged reads and write are not disabled by this mechanism.
0b1	Disables privileged read and write accesses to addresses accessible at EL0 for an enabled stage 1 translation regime that defines the EL0 permissions.

The value of this bit is usually preserved on taking an exception, except in the following situations:

When the target of the exception is EL1, and the value of the SCTLR_EL1.SPAN bit is 0, this bit is set to 1.
When the target of the exception is EL2, the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, and the value of the SCTLR_EL2.SPAN bit is 0, this bit is set to 1.

Bits [21:0]

Accessing PAN

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PAN

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0010	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = Zeros(41):PSTATE.PAN:Zeros(22); elsif PSTATE.EL == EL2 then X[t, 64] = Zeros(41):PSTATE.PAN:Zeros(22); elsif PSTATE.EL == EL3 then X[t, 64] = Zeros(41):PSTATE.PAN:Zeros(22);

MSR PAN, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0010	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.PAN = X[t, 64]<22>; elsif PSTATE.EL == EL2 then PSTATE.PAN = X[t, 64]<22>; elsif PSTATE.EL == EL3 then PSTATE.PAN = X[t, 64]<22>;

MSR PAN, #<imm>

op0	op1	CRn	op2
0b00	0b000	0b0100	0b100

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0									PAN	RES0

PAN, Privileged Access Never

Purpose

Configuration