PMECR_EL1

This register is present only when FEAT_EBEP is implemented or FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMECR_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:5]

SSE, bits [4:3]
When FEAT_PMUv3_SS is implemented:

Snapshot Enable. Controls the generation of Capture events.

SSE	Meaning
0b00	Capture events are disabled.
0b10	Capture events are enabled and prohibited.
0b11	Capture events are enabled and allowed.

All other values are reserved.

The reset behavior of this field is:

On a Cold reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

KPME, bit [2]
When FEAT_EBEP is implemented:

KPME	Meaning
0b0	PMU exceptions taken to the current Exception level are disabled.
0b1	PMU exceptions taken to the current Exception level are not affected by this field.

Otherwise:

PMEE, bits [1:0]
When FEAT_EBEP is implemented:

Performance Monitors Exception Enable. Controls the generation of PMUIRQ signal and PMU exception at EL0 and EL1.

PMEE	Meaning
0b00	PMUIRQ signal is enabled, and PMU exception is disabled.
0b10	PMUIRQ signal is disabled, and PMU exception is disabled.
0b11	PMUIRQ signal is disabled, and PMU exception is enabled.

All other values are reserved.

This field is ignored by the PE when any of the following are true:

All of the following are true:
- EL3 is implemented.
- MDCR_EL3.PMEE != 0b01.
All of the following are true:
- EL2 is implemented and enabled in the current Security State.
- MDCR_EL2.PMEE != 0b01.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing PMECR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMECR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1110	0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGRTR2_EL2.nPMECR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMECR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMECR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMECR_EL1;

MSR PMECR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1110	0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGWTR2_EL2.nPMECR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMECR_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
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RES0
RES0																											SSE		KPME	PMEE

PMECR_EL1, Performance Monitors Extended Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:5]

SSE, bits [4:3]
When FEAT_PMUv3_SS is implemented:

Otherwise:

KPME, bit [2]
When FEAT_EBEP is implemented:

Otherwise:

PMEE, bits [1:0]
When FEAT_EBEP is implemented:

Otherwise:

Accessing PMECR_EL1

MRS <Xt>, PMECR_EL1

MSR PMECR_EL1, <Xt>

PMECR_EL1, Performance Monitors Extended Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:5]

SSE, bits [4:3]When FEAT_PMUv3_SS is implemented:

Otherwise:

KPME, bit [2]When FEAT_EBEP is implemented:

Otherwise:

PMEE, bits [1:0]When FEAT_EBEP is implemented:

Otherwise:

Accessing PMECR_EL1

MRS <Xt>, PMECR_EL1

MSR PMECR_EL1, <Xt>

SSE, bits [4:3]
When FEAT_PMUv3_SS is implemented:

KPME, bit [2]
When FEAT_EBEP is implemented:

PMEE, bits [1:0]
When FEAT_EBEP is implemented: