SPSR_EL2

AArch64 System register SPSR_EL2 bits [31:0] are architecturally mapped to AArch32 System register SPSR_hyp[31:0].

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

When AArch32 is supported and exception taken from AArch32 state:

Bits [63:34]

PPEND, bit [33]
When FEAT_SEBEP is implemented:

Otherwise:

Bit [32]

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Q, bit [27]

IT, bits [15:10, 26:25]

If-Then. Set to the value of PSTATE.IT on taking an exception to EL2, and copied to PSTATE.IT on executing an exception return operation in EL2.

SPSR_EL2.IT must contain a value that is valid for the instruction being returned to.

The IT field is split as follows:

IT[1:0] is SPSR_EL2[26:25].
IT[7:2] is SPSR_EL2[15:10].

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

DIT, bit [24]
When FEAT_DIT is implemented:

Otherwise:

SSBS, bit [23]
When FEAT_SSBS is implemented:

Otherwise:

PAN, bit [22]
When FEAT_PAN is implemented:

Otherwise:

SS, bit [21]

IL, bit [20]

GE, bits [19:16]

E, bit [9]

Endianness. Set to the value of PSTATE.E on taking an exception to EL2, and copied to PSTATE.E on executing an exception return operation in EL2.

If the implementation does not support big-endian operation, SPSR_EL2.E is RES0. If the implementation does not support little-endian operation, SPSR_EL2.E is RES1. On executing an exception return operation in EL2, if the implementation does not support big-endian operation at the Exception level being returned to, SPSR_EL2.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, SPSR_EL2.E is RES1.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

A, bit [8]

I, bit [7]

F, bit [6]

T, bit [5]

M[4], bit [4]

M[3:0], bits [3:0]

M[4]	Meaning
0b1	AArch32 execution state.

AArch32 Mode. Set to the value of PSTATE.M[3:0] on taking an exception to EL2, and copied to PSTATE.M[3:0] on executing an exception return operation in EL2.

M[3:0]	Meaning
0b0000	User.
0b0001	FIQ.
0b0010	IRQ.
0b0011	Supervisor.
0b0111	Abort.
0b1010	Hyp.
0b1011	Undefined.
0b1111	System.

Other values are reserved. If SPSR_EL2.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, executing an exception return operation in EL2 is an illegal return event, as described in 'Illegal return events from AArch64 state'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When exception taken from AArch64 state:

Bits [63:36]

PACM, bit [35]
When FEAT_PAuth_LR is implemented:

Otherwise:

EXLOCK, bit [34]
When FEAT_GCS is implemented:

Otherwise:

PPEND, bit [33]
When FEAT_SEBEP is implemented:

Otherwise:

PM, bit [32]
When FEAT_EBEP is implemented:

Otherwise:

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Bits [27:26]

TCO, bit [25]
When FEAT_MTE is implemented:

Otherwise:

DIT, bit [24]
When FEAT_DIT is implemented:

Otherwise:

UAO, bit [23]
When FEAT_UAO is implemented:

Otherwise:

PAN, bit [22]
When FEAT_PAN is implemented:

Otherwise:

SS, bit [21]

IL, bit [20]

Bits [19:14]

ALLINT, bit [13]
When FEAT_NMI is implemented:

Otherwise:

SSBS, bit [12]
When FEAT_SSBS is implemented:

Otherwise:

BTYPE, bits [11:10]
When FEAT_BTI is implemented:

Otherwise:

D, bit [9]

A, bit [8]

I, bit [7]

F, bit [6]

Bit [5]

M[4], bit [4]

M[3:0], bits [3:0]

M[4]	Meaning
0b0	AArch64 execution state.

AArch64 Exception level and selected Stack Pointer.

M[3:0]	Meaning
0b0000	EL0.
0b0100	EL1 with SP_EL0 (EL1t).
0b0101	EL1 with SP_EL1 (EL1h).
0b1000	EL2 with SP_EL0 (EL2t).
0b1001	EL2 with SP_EL2 (EL2h).

The bits in this field are interpreted as follows:

M[3:2] is set to the value of PSTATE.EL on taking an exception to EL2 and copied to PSTATE.EL on executing an exception return operation in EL2.
M[1] is unused and is 0 for all non-reserved values.
M[0] is set to the value of PSTATE.SP on taking an exception to EL2 and copied to PSTATE.SP on executing an exception return operation in EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing SPSR_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name SPSR_EL2 or SPSR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPSR_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0100	0b0000	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = SPSR_EL1; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = SPSR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = SPSR_EL2;

MSR SPSR_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0100	0b0000	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && EffectiveHCR_EL2_NVx() IN {'xx1'} then EXLOCKException(); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then SPSR_EL1 = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' then EXLOCKException(); else SPSR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then SPSR_EL2 = X[t, 64];

When FEAT_VHE is implemented

MRS <Xt>, SPSR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0000	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x160]; else X[t, 64] = SPSR_EL1; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = SPSR_EL2; else X[t, 64] = SPSR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = SPSR_EL1;

When FEAT_VHE is implemented

MSR SPSR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0000	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && !(EffectiveHCR_EL2_NVx() IN {'x11'}) then EXLOCKException(); elsif EffectiveHCR_EL2_NVx() == '011' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x160] = X[t, 64]; else SPSR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && ELIsInHost(EL2) then EXLOCKException(); elsif ELIsInHost(EL2) then SPSR_EL2 = X[t, 64]; else SPSR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then SPSR_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																														PPEND	RES0
N	Z	C	V	Q	IT[1:0]		DIT	SSBS	PAN	SS	IL	GE				IT[7:2]						E	A	I	F	T	M[4]	M[3:0]

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																												PACM	EXLOCK	PPEND	PM
N	Z	C	V	RES0		TCO	DIT	UAO	PAN	SS	IL	RES0						ALLINT	SSBS	BTYPE		D	A	I	F	RES0	M[4]	M[3:0]

SPSR_EL2, Saved Program Status Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

When AArch32 is supported and exception taken from AArch32 state:

Bits [63:34]

PPEND, bit [33]When FEAT_SEBEP is implemented:

Otherwise:

Bit [32]

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Q, bit [27]

IT, bits [15:10, 26:25]

DIT, bit [24]When FEAT_DIT is implemented:

Otherwise:

SSBS, bit [23]When FEAT_SSBS is implemented:

Otherwise:

PAN, bit [22]When FEAT_PAN is implemented:

Otherwise:

SS, bit [21]

IL, bit [20]

GE, bits [19:16]

E, bit [9]

A, bit [8]

I, bit [7]

F, bit [6]

T, bit [5]

M[4], bit [4]

M[3:0], bits [3:0]

When exception taken from AArch64 state:

Bits [63:36]

PACM, bit [35]When FEAT_PAuth_LR is implemented:

Otherwise:

EXLOCK, bit [34]When FEAT_GCS is implemented:

Otherwise:

PPEND, bit [33]When FEAT_SEBEP is implemented:

Otherwise:

PM, bit [32]When FEAT_EBEP is implemented:

Otherwise:

N, bit [31]

Z, bit [30]

C, bit [29]

V, bit [28]

Bits [27:26]

TCO, bit [25]When FEAT_MTE is implemented:

Otherwise:

DIT, bit [24]When FEAT_DIT is implemented:

Otherwise:

UAO, bit [23]When FEAT_UAO is implemented:

Otherwise:

PAN, bit [22]When FEAT_PAN is implemented:

Otherwise:

SS, bit [21]

IL, bit [20]

Bits [19:14]

ALLINT, bit [13]When FEAT_NMI is implemented:

Otherwise:

SSBS, bit [12]When FEAT_SSBS is implemented:

Otherwise:

BTYPE, bits [11:10]When FEAT_BTI is implemented:

Otherwise:

D, bit [9]

A, bit [8]

I, bit [7]

F, bit [6]

Bit [5]

M[4], bit [4]

M[3:0], bits [3:0]

Accessing SPSR_EL2

MRS <Xt>, SPSR_EL2

MSR SPSR_EL2, <Xt>

When FEAT_VHE is implemented

MRS <Xt>, SPSR_EL1

When FEAT_VHE is implemented

MSR SPSR_EL1, <Xt>

PPEND, bit [33]
When FEAT_SEBEP is implemented:

DIT, bit [24]
When FEAT_DIT is implemented:

SSBS, bit [23]
When FEAT_SSBS is implemented:

PAN, bit [22]
When FEAT_PAN is implemented:

PACM, bit [35]
When FEAT_PAuth_LR is implemented:

EXLOCK, bit [34]
When FEAT_GCS is implemented:

PPEND, bit [33]
When FEAT_SEBEP is implemented:

PM, bit [32]
When FEAT_EBEP is implemented:

TCO, bit [25]
When FEAT_MTE is implemented:

DIT, bit [24]
When FEAT_DIT is implemented:

UAO, bit [23]
When FEAT_UAO is implemented:

PAN, bit [22]
When FEAT_PAN is implemented:

ALLINT, bit [13]
When FEAT_NMI is implemented:

SSBS, bit [12]
When FEAT_SSBS is implemented:

BTYPE, bits [11:10]
When FEAT_BTI is implemented: