The TLBI RVAE3OS, TLBI RVAE3OSNXS characteristics are:
If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 64-bit stage 1 translation table entry, from any level of the translation table walk up to the level indicated in the TTL hint.
If FEAT_D128 is implemented, a 128-bit stage 1 translation table entry, if TTL is 0b00.
The entry would be used to translate any of the VAs in the specified address range using the EL3 translation regime.
The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].
The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.
For 64-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when:
For the 4K translation granule:
For the 16K translation granule:
For the 64K translation granule:
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
This instruction is present only when FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented. Otherwise, direct accesses to TLBI RVAE3OS, TLBI RVAE3OSNXS are UNDEFINED.
TLBI RVAE3OS, TLBI RVAE3OSNXS is a 64-bit System instruction.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | TG | SCALE | NUM | TTL | BaseADDR | ||||||||||||||||||||||||||
| BaseADDR | |||||||||||||||||||||||||||||||
Reserved, RES0.
Translation granule size.
| TG | Meaning |
|---|---|
| 0b00 |
Reserved. |
| 0b01 |
4K translation granule. |
| 0b10 |
16K translation granule. |
| 0b11 |
64K translation granule. |
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
The exponent element of the calculation that is used to produce the upper range.
The base element of the calculation that is used to produce the upper range.
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
| TTL | Meaning |
|---|---|
| 0b00 |
The entries in the range can be using any level for the translation table entries. |
| 0b01 | The TTL hint indicates level 1. If FEAT_LPA2 is not implemented, when using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00. |
| 0b10 |
The TTL hint indicates level 2. |
| 0b11 |
The TTL hint indicates level 3. |
The starting address for the range of the maintenance instructions. This field is BaseADDR[52:16] for all translation granules.
When using a 4KB translation granule, BaseADDR[15:12] is treated as 0b0000.
When using a 16KB translation granule, BaseADDR[15:14] is treated as 0b00.
The starting address for the range of the maintenance instruction.
When using a 4KB translation granule, this field is BaseADDR[48:12].
When using a 16KB translation granule, this field is BaseADDR[50:14].
When using a 64KB translation granule, this field is BaseADDR[52:16].
Accesses to this instruction use the following encodings in the System instruction encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b110 | 0b1000 | 0b0101 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3) then return; else AArch64.TLBI_RVA(SecurityStateAtEL(EL3), Regime_EL3, VMID[], Shareability_OSH, TLBILevel_Any, TLBI_AllAttr, X[t, 64]);
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b110 | 0b1001 | 0b0101 | 0b001 |
if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3) then return; else AArch64.TLBI_RVA(SecurityStateAtEL(EL3), Regime_EL3, VMID[], Shareability_OSH, TLBILevel_Any, TLBI_ExcludeXS, X[t, 64]);
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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