TRBMAR_EL1, Trace Buffer Memory Attribute Register

The TRBMAR_EL1 characteristics are:

Purpose

Controls Trace Buffer Unit accesses to memory.

If the trace buffer pointers specify virtual addresses, the address properties are defined by the translation tables and this register is ignored.

Configuration

AArch64 System register TRBMAR_EL1 bits [63:0] are architecturally mapped to External register TRBMAR_EL1[63:0] when FEAT_TRBE_EXT is implemented.

This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBMAR_EL1 are UNDEFINED.

Attributes

TRBMAR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0PASSHAttr

Bits [63:12]

Reserved, RES0.

PAS, bits [11:10]
When FEAT_TRBE_EXT is implemented:

Physical address specifier. Defines the PAS attribute for memory addressed by the buffer in External mode.

PASMeaningApplies when
0b00

Secure.

When Secure state is implemented
0b01

Non-secure.

0b10

Root.

When FEAT_RME is implemented
0b11

Realm.

When FEAT_RME is implemented

All other values are reserved.

If the Trace Buffer Unit is using external mode and either TRBMAR_EL1.PAS is set to a reserved value, or the IMPLEMENTATION DEFINED authentication interface prohibits invasive debug of the Security state corresponding to the physical address space selected by TRBMAR_EL1.PAS, then when the Trace Buffer Unit receives trace data from the trace unit, it does not write the trace data to memory and generates a trace buffer management event. That is, if any of the following apply:

This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SH, bits [9:8]

Trace buffer shareability domain. Defines the shareability domain for Normal memory used by the trace buffer.

SHMeaning
0b00

Non-shareable.

0b10

Outer Shareable.

0b11

Inner Shareable.

All other values are reserved.

This field is ignored when TRBMAR_EL1.Attr specifies any of the following memory types:

All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.

The reset behavior of this field is:

Attr, bits [7:0]
When TRBMAR_EL1.Attr IN {0bxxxx0000}:

Trace buffer memory type and attributes. Defines the memory type and, for Normal memory, the cacheability attributes, for memory addressed by the trace buffer.

AttrMeaningApplies when
0x00

Device-nGnRnE memory.

0x40

Normal memory, Inner Non-cacheable, Outer Non-cacheable with the XS attribute set to 0.

When FEAT_XS is implemented
0xA0

Normal memory, Inner Write-through Cacheable, Outer Write-through Cacheable, Non-transient, Read-Allocate with the XS attribute set to 0.

When FEAT_XS is implemented
0xF0

Tagged Normal memory, Outer Write-Back Non-transient, Read-allocate Write-allocate.

When FEAT_MTE2 is implemented

All other values are reserved.

The reset behavior of this field is:


When TRBMAR_EL1.Attr IN {0b0000xxxx} and TRBMAR_EL1.Attr != 0b00000000:

Trace buffer memory attributes. Defines the Device memory attributes for memory addressed by the trace buffer.

AttrMeaningApplies when
0x04

Device-nGnRE memory.

0x08

Device-nGRE memory.

0x0C

Device-GRE memory.

0x01

Device-nGnRnE memory with the XS attribute set to 0.

When FEAT_XS is implemented
0x05

Device-nGnRE memory with the XS attribute set to 0.

When FEAT_XS is implemented
0x09

Device-nGRE memory with the XS attribute set to 0.

When FEAT_XS is implemented
0x0D

Device-GRE memory with the XS attribute set to 0.

When FEAT_XS is implemented

All other values are reserved.

The reset behavior of this field is:


When !(TRBMAR_EL1.Attr IN {0bxxxx0000}) and !(TRBMAR_EL1.Attr IN {0b0000xxxx}):

Trace buffer memory type and attributes. Defines the memory type and, for Normal memory, the Outer and Inner cacheability attributes, for memory addressed by the trace buffer.

AttrMeaning
0b0001xxxx

Normal memory, Outer Write-Through Transient, Write-allocate.

0b0010xxxx

Normal memory, Outer Write-Through Transient, Read-allocate.

0b0011xxxx

Normal memory, Outer Write-Through Transient, Read-allocate Write-allocate.

0b0100xxxx

Normal memory, Outer Non-cacheable.

0b0101xxxx

Normal memory, Outer Write-Back Transient, Write-allocate.

0b0110xxxx

Normal memory, Outer Write-Back Transient, Read-allocate.

0b0111xxxx

Normal memory, Outer Write-Back Transient, Read-allocate Write-allocate.

0b1000xxxx

Normal memory, Outer Write-Through Non-transient, No allocate.

0b1001xxxx

Normal memory, Outer Write-Through Non-transient, Write-allocate.

0b1010xxxx

Normal memory, Outer Write-Through Non-transient, Read-allocate.

0b1011xxxx

Normal memory, Outer Write-Through Non-transient, Read-allocate Write-allocate.

0b1100xxxx

Normal memory, Outer Write-Back Non-transient, No allocate.

0b1101xxxx

Normal memory, Outer Write-Back Non-transient, Write-allocate.

0b1110xxxx

Normal memory, Outer Write-Back Non-transient, Read-allocate.

0b1111xxxx

Normal memory, Outer Write-Back Non-transient, Read-allocate Write-allocate.

0bxxxx0001

Normal memory, Inner Write-Through Transient, Write-allocate.

0bxxxx0010

Normal memory, Inner Write-Through Transient, Read-allocate.

0bxxxx0011

Normal memory, Inner Write-Through Transient, Read-allocate Write-allocate.

0bxxxx0100

Normal memory, Inner Non-cacheable.

0bxxxx0101

Normal memory, Inner Write-Back Transient, Write-allocate.

0bxxxx0110

Normal memory, Inner Write-Back Transient, Read-allocate.

0bxxxx0111

Normal memory, Inner Write-Back Transient, Read-allocate Write-allocate.

0bxxxx1000

Normal memory, Inner Write-Through Non-transient, No allocate.

0bxxxx1001

Normal memory, Inner Write-Through Non-transient, Write-allocate.

0bxxxx1010

Normal memory, Inner Write-Through Non-transient, Read-allocate.

0bxxxx1011

Normal memory, Inner Write-Through Non-transient, Read-allocate Write-allocate.

0bxxxx1100

Normal memory, Inner Write-Back Non-transient, No allocate.

0bxxxx1101

Normal memory, Inner Write-Back Non-transient, Write-allocate.

0bxxxx1110

Normal memory, Inner Write-Back Non-transient, Read-allocate.

0bxxxx1111

Normal memory, Inner Write-Back Non-transient, Read-allocate Write-allocate.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing TRBMAR_EL1

The PE might ignore a write to TRBMAR_EL1 if any of the following apply:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRBMAR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBMAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRBMAR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRBMAR_EL1; elsif PSTATE.EL == EL3 then if !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRBMAR_EL1;

MSR TRBMAR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10110b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRBMAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then if !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMAR_EL1 = X[t, 64];


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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