The CTIDEVAFF0 characteristics are:
Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the CTI component relates to.
CTIDEVAFF0 is in the Debug power domain.
If the CTI is CTIv1, this register is OPTIONAL. If the CTI is CTIv2, this register is mandatory.
Arm recommends that the CTI is CTIv2.
In an Armv8.5 compliant implementation, the CTI must be CTIv2.
If this register is implemented, then CTIDEVAFF1 must also be implemented. If the CTI of a PE does not implement the CTI Device Affinity registers, the CTI block of the external debug memory map must be located 64KB above the debug registers in the external debug interface.
CTIDEVAFF0 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPIDR_EL1lo | |||||||||||||||||||||||||||||||
MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1, as seen from the highest implemented Exception level.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| CTI | 0xFA8 | CTIDEVAFF0 |
Accesses on this interface are RO.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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