The CTIPIDR0 characteristics are:
Provides information to identify a CTI component.
For more information, see 'About the Peripheral identification scheme'.
CTIPIDR0 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTIPIDR0 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PART_0 | ||||||||||||||||||||||||||||||
Reserved, RES0.
Part number, least significant byte.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| CTI | 0xFE0 | CTIPIDR0 |
Accesses on this interface are RO.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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