The ERRCIDR1 characteristics are:
Provides discovery information about the component.
For more information, see 'About the Component Identification scheme'.
Implementation of this register is OPTIONAL.
ERRCIDR1 is implemented only as part of a memory-mapped group of error records.
ERRCIDR1 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | CLASS | PRMBL_1 | |||||||||||||||||||||||||||||
Reserved, RES0.
Component class.
| CLASS | Meaning |
|---|---|
| 0b1111 |
Generic peripheral with IMPLEMENTATION DEFINED register layout. |
Other values are defined by the CoreSight Architecture.
This field reads as 0xF.
Access to this field is RO.
Component identification preamble, segment 1.
Reads as 0b0000.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| RAS | 0xFF4 | ERRCIDR1 |
Accesses on this interface are RO.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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