The GICD_NSACR<n>E characteristics are:
Enables Secure software to permit Non-secure software on a particular PE to create and control Group 0 interrupts.
This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_NSACR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ICFGR<n>E registers is ((GICD_TYPER.ESPI_range+1)*2). Registers are numbered from 0.
GICD_NSACR<n>E is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS_access15 | NS_access14 | NS_access13 | NS_access12 | NS_access11 | NS_access10 | NS_access9 | NS_access8 | NS_access7 | NS_access6 | NS_access5 | NS_access4 | NS_access3 | NS_access2 | NS_access1 | NS_access0 |
Controls Non-secure access of the interrupt with ID 16n + x.
If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI.
Otherwise, the field is RW and determines the level of Non-secure control permitted if the interrupt is a Secure interrupt. If the interrupt is a Non-secure interrupt, this field is ignored.
The possible values of each 2-bit field are:
NS_access<x> | Meaning |
---|---|
0b00 |
No Non-secure access is permitted to fields associated with the corresponding interrupt. |
0b01 |
Non-secure read and write access is permitted to set-pending bits in GICD_ISPENDR<n>E associated with the corresponding interrupt. A Non-secure write access to GICD_SETSPI_NSR is permitted to set the pending state of the corresponding interrupt. |
0b10 |
As 0b01, but adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDR<n>E registers. A Non-secure write access to GICD_CLRSPI_NSR is permitted to clear the pending state of the corresponding interrupt. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVER<n>E and GICD_ICACTIVER<n>E registers. |
0b11 |
This encoding is treated as 0b10, but adds Non-secure read and write access permission to GICD_IROUTER<n>E fields associated with the corresponding interrupt. |
The reset behavior of this field is:
For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | Dist_base | 0x3600 + (4 * n) | GICD_NSACR<n>E |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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