GICH_EISR, End Interrupt Status Register

The GICH_EISR characteristics are:

Purpose

Indicates which List registers have outstanding EOI maintenance interrupts.

This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICH_EISR are RES0.

This register is available when the GIC implementation supports interrupt virtualization.

GICH_EISR is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																Status15	Status14	Status13	Status12	Status11	Status10	Status9	Status8	Status7	Status6	Status5	Status4	Status3	Status2	Status1	Status0

Reserved, RES0.

EOI maintenance interrupt status for List register <n>:

Status<n>	Meaning
0b0	GICH_LR<n> does not have an EOI maintenance interrupt.
0b1	GICH_LR<n> has an EOI maintenance interrupt that has not been handled.

For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:

The reset behavior of this field is:

This register is used only when System register access is not enabled. When System register access is enabled:

Bits corresponding to unimplemented List registers are RAZ.

Component	Offset	Instance
GIC Virtual interface control	0x0020	GICH_EISR

This interface is accessible as follows:

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6