The GICR_IGRPMODR<n>E characteristics are:
When GICD_CTLR.DS==0, this register together with the GICR_IGROUPR<n>E registers, controls whether the corresponding interrupt is in:
This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICR_IGRPMODR<n>E are RES0.
When GICD_CTLR.DS==0, this register is Secure.
A copy of this register is provided for each Redistributor.
GICR_IGRPMODR<n>E is a 32-bit register.
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGROUPR<n>E to form a 2-bit field that defines an interrupt group:
| Group modifier bit | Group status bit | Definition | Short name |
|---|---|---|---|
| 0b0 | 0b0 | Secure Group 0 | G0S |
| 0b0 | 0b1 | Non-secure Group 1 | G1NS |
| 0b1 | 0b0 | Secure Group 1 | G1S |
| 0b1 | 0b1 | Reserved, treated as Non-secure Group 1 | - |
The reset behavior of this field is:
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICR_IGRPMODR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | SGI_base | 0x0D00 + (4 * n) | GICR_IGRPMODR<n>E |
Accesses on this interface are RW.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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