GICR_ISACTIVER<n>E, Interrupt Set-Active Registers, n = 1 - 2

The GICR_ISACTIVER<n>E characteristics are:

Purpose

Adds the active state to the corresponding PPI.

Configuration

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICR_ISACTIVER<n>E are RES0.

A copy of this register is provided for each Redistributor.

Attributes

GICR_ISACTIVER<n>E is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
Set_active_bit31Set_active_bit30Set_active_bit29Set_active_bit28Set_active_bit27Set_active_bit26Set_active_bit25Set_active_bit24Set_active_bit23Set_active_bit22Set_active_bit21Set_active_bit20Set_active_bit19Set_active_bit18Set_active_bit17Set_active_bit16Set_active_bit15Set_active_bit14Set_active_bit13Set_active_bit12Set_active_bit11Set_active_bit10Set_active_bit9Set_active_bit8Set_active_bit7Set_active_bit6Set_active_bit5Set_active_bit4Set_active_bit3Set_active_bit2Set_active_bit1Set_active_bit0

Set_active_bit<x>, bit [x], for x = 31 to 0

For the extended PPIs, adds the active state to interrupt number x. Reads and writes have the following behavior:

Set_active_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not active, and is not active and pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is active, or active and pending on this PE.

If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect.

After a write of 1 to this bit, a subsequent read of this bit returns 1.

The reset behavior of this field is:

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

Accessing GICR_ISACTIVER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISACTIVER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICR_ISACTIVER<n>E can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0300 + (4 * n)GICR_ISACTIVER<n>E

Accesses on this interface are RW.


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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