GICR_ISENABLER<n>E

Set_enable_bit<x>	Meaning
0b0	If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect.
0b1	If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1.

Set_enable_bit<x>

Meaning

0b0

If read, indicates that forwarding of the corresponding interrupt is disabled.

If written, has no effect.

0b1

If read, indicates that forwarding of the corresponding interrupt is enabled.

If written, enables forwarding of the corresponding interrupt.

After a write of 1 to this bit, a subsequent read of this bit returns 1.

The reset behavior of this field is:

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICR_ISENABLER<n>E number, n, is given by n = (m-1024) DIV 32.
The offset of the required GICR_ISENABLER<n>E is (0x100 + (4*n)).
The bit number of the required group modifier bit in this register is (m-1024) MOD 32.

Accessing GICR_ISENABLER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISENABLER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

GICR_ISENABLER<n>E can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Redistributor	SGI_base	0x0100 + (4 * n)	GICR_ISENABLER<n>E

Component

Frame

Offset

Instance

GIC Redistributor

SGI_base

0x0100 + (4 * n)

GICR_ISENABLER<n>E

GICR_ISENABLER<n>E, Interrupt Set-Enable Registers, n = 1 - 2