The GICV_RPR characteristics are:
This register indicates the running priority of the virtual CPU interface.
This register corresponds to the physical CPU interface register GICC_RPR.
This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICV_RPR are RES0.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_RPR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Priority |
Reserved, RES0.
The current running priority on the virtual CPU interface. This is the group priority of the current active interrupt.
If there are no active interrupts on the CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.
The priority returned is the group priority as if the BPR was set to the minimum value.
This register is used only when System register access is not enabled. When System register access is enabled:
Depending on the implementation, if no bits are set to 1 in GICH_APR<n>, indicating no active virtual interrupts in the virtual CPU interface, the priority reads as 0xFF or 0xF8 to reflect the number of supported interrupt priority bits defined by GICH_VTR.PRIbits.
Component | Offset | Instance |
---|---|---|
GIC Virtual CPU interface | 0x0014 | GICV_RPR |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.