GITS_BASER<n>, ITS Table Descriptors, n = 0 - 7

The GITS_BASER<n> characteristics are:

Purpose

Specifies the base address and size of the ITS tables.

Configuration

A copy of this register is provided for each ITS table.

Bits [63:32] and bits [31:0] are accessible independently.

A maximum of 8 GITS_BASER<n> registers can be provided. Unimplemented registers are RES0.

When GITS_CTLR.Enabled == 1 or GITS_CTLR.Quiescent == 0, writing this register is UNPREDICTABLE.

Attributes

GITS_BASER<n> is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ValidIndirectInnerCacheTypeOuterCacheEntry_SizePhysical_Address
Physical_AddressShareabilityPage_SizeSize

Valid, bit [63]

Indicates whether software has allocated memory for the table:

ValidMeaning
0b0

No memory is allocated for the table. The ITS discards any writes to the interrupt translation page when either:

  • GITS_BASER<n>.Type specifies any valid table entry type other than interrupt collections, that is, any value other than 0b100.
  • GITS_BASER<n>.Type specifies an interrupt collection and GITS_TYPER.HCC == 0.
0b1

Memory is allocated to the table.

The reset behavior of this field is:

Indirect, bit [62]

This field indicates whether an implemented register specifies a single, flat table or a two-level table where the first level contains a list of descriptors.

IndirectMeaning
0b0

Single Level. The Size field indicates the number of pages used by the ITS to store data associated with each table entry.

0b1

Two Level. The Size field indicates the number of pages which contain an array of 64-bit descriptors to pages that are used to store the data associated with each table entry. A little endian memory order model is used.

For more information, see 'The ITS tables' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

This field is RAZ/WI for GIC implementations that only support flat tables. If the maximum width of the scaling factor that is identified by GITS_BASER<n>.Type and the smallest page size that is supported result in a single level table that requires multiple pages, then implementing this bit as RAZ/WI is DEPRECATED.

The reset behavior of this field is:

InnerCache, bits [61:59]

Indicates the Inner Cacheability attributes of accesses to the table. The possible values of this field are:

InnerCacheMeaning
0b000

Device-nGnRnE.

0b001

Normal Inner Non-cacheable.

0b010

Normal Inner Cacheable Read-allocate, Write-through.

0b011

Normal Inner Cacheable Read-allocate, Write-back.

0b100

Normal Inner Cacheable Write-allocate, Write-through.

0b101

Normal Inner Cacheable Write-allocate, Write-back.

0b110

Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.

0b111

Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

The reset behavior of this field is:

Type, bits [58:56]

Read only. Specifies the type of entity that requires entries in the corresponding table. The possible values of the field are:

TypeMeaning
0b000

Unimplemented. This register does not correspond to an ITS table.

0b001

Devices. This register corresponds to an ITS table that scales with the width of the DeviceID. Only a single GITS_BASER<n> register reports this type.

0b010

vPEs. FEAT_GICv4 only. This register corresponds to an ITS table that scales with the number of vPEs in the system. The table requires (ENTRY_SIZE * N) bytes of memory, where N is the number of vPEs in the system. Only a single GITS_BASER<n> register reports this type.

0b100

Interrupt collections. This register corresponds to an ITS table that scales with the number of interrupt collections in the system. The table requires (ENTRY_SIZE * N) bytes of memory, where N is the number of interrupt collections. Not more than one GITS_BASER<n> register will report this type.

Other values are reserved.

For FEAT_GICv4p1, the registers are allocated as follows:

For FEAT_GICv3, FEAT_GICv3p1, and FEAT_GICv4, Arm recommends that the GITS_BASER<n> use the same allocations.

Other allocations of Type values are deprecated.

OuterCache, bits [55:53]

Indicates the Outer Cacheability attributes of accesses to the table. The possible values of this field are:

OuterCacheMeaning
0b000

Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.

0b001

Normal Outer Non-cacheable.

0b010

Normal Outer Cacheable Read-allocate, Write-through.

0b011

Normal Outer Cacheable Read-allocate, Write-back.

0b100

Normal Outer Cacheable Write-allocate, Write-through.

0b101

Normal Outer Cacheable Write-allocate, Write-back.

0b110

Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.

0b111

Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The reset behavior of this field is:

Entry_Size, bits [52:48]

Read-only. Specifies the number of bytes per table entry, minus one.

Physical_Address, bits [47:12]

Physical Address. When Page_Size is 4KB or 16KB:

When Page_Size is 64KB:

In implementations that support fewer than 52 bits of physical address, any unimplemented upper bits might be RAZ/WI.

The reset behavior of this field is:

Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the table. The possible values of this field are:

ShareabilityMeaning
0b00

Non-shareable.

0b01

Inner Shareable.

0b10

Outer Shareable.

0b11

Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The reset behavior of this field is:

Page_Size, bits [9:8]

The size of page that the table uses:

Page_SizeMeaning
0b00

4KB.

0b01

16KB.

0b10

64KB.

0b11

Reserved. Treated as 0b10.

Note

If the GIC implementation supports only a single, fixed page size, this field might be RO.

The reset behavior of this field is:

Size, bits [7:0]

The number of pages of physical memory allocated to the table, minus one. GITS_BASER<n>.Page_Size specifies the size of each page.

If GITS_BASER<n>.Type == 0, this field is RAZ/WI.

The reset behavior of this field is:

Accessing GITS_BASER<n>

GITS_BASER<n> can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC ITS control0x0100 + (8 * n)GITS_BASER<n>

Accesses on this interface are RW.


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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