TRBMPAM

Defines the PARTID, PMG, and MPAM_SP values used by the trace buffer unit in external mode.

Configuration

External register TRBMPAM_EL1 bits [63:0] are architecturally mapped to AArch64 System register TRBMPAM_EL1[63:0].

This register is present only when FEAT_TRBE_EXT is implemented and FEAT_TRBE_MPAM is implemented. Otherwise, direct accesses to TRBMPAM_EL1 are RES0.

Attributes

Field descriptions

Bits [63:27]

EN, bit [26]

Enable. Enables use of non-default MPAM values.

EN	Meaning
0b0	Use default MPAM values.
0b1	Use TRBMPAM_EL1.{PARTID, PMG, MPAM_SP}.

This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.

The reset behavior of this field is:

On a Cold reset, this field resets to 0.

MPAM_SP, bits [25:24]

Partition Identifier space. Selects the PARTID space.

MPAM_SP	Meaning	Applies when
0b00	PARTID is in the Secure PARTID space.	When Secure state is implemented
0b01	PARTID is in the Non-secure PARTID space.
0b10	PARTID is in the Root PARTID space.	When FEAT_RME is implemented
0b11	PARTID is in the Realm PARTID space.	When FEAT_RME is implemented

All other values are reserved.

If the Trace Buffer Unit is using external mode and either TRBMPAM_EL1.MPAM_SP is set to reserved value, or the IMPLEMENTATION DEFINED authentication interface prohibits invasive debug of the Security state corresponding to the Partition Identifier space selected by TRBMPAM_EL1.MPAM_SP, then when the Trace Buffer Unit receives trace data from the trace unit, it does not write the trace data to memory and generates a trace buffer management event. That is, if any of the following apply:

ExternalInvasiveDebugEnabled() == FALSE.
TRBMPAM_EL1.MPAM_SP is 0b00, and either ExternalSecureInvasiveDebugEnabled() == FALSE or Secure state is not implemented.
TRBMPAM_EL1.MPAM_SP is 0b10, and either ExternalRootInvasiveDebugEnabled() == FALSE or FEAT_RME is not implemented.
TRBMPAM_EL1.MPAM_SP is 0b11, and either ExternalRealmInvasiveDebugEnabled() == FALSE or FEAT_RME is not implemented.

This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

PMG, bits [23:16]

Performance Monitoring Group. Selects the PMG.

Only sufficient low-order bits are required to represent the TRBDEVID1.PMG_MAX. Higher-order bits are RES0.

This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

PARTID, bits [15:0]

Partition Identifier. Selects the PARTID.

Only sufficient low-order bits are required to represent the TRBDEVID1.PARTID_MAX. Higher-order bits are RES0.

This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing TRBMPAM_EL1

TRBMPAM_EL1 can be accessed through the external debug interface:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0					EN	MPAM_SP		PMG								PARTID

TRBMPAM_EL1, Trace Buffer MPAM Configuration Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:27]

EN, bit [26]

MPAM_SP, bits [25:24]

PMG, bits [23:16]

PARTID, bits [15:0]

Accessing TRBMPAM_EL1

TRBMPAM_EL1 can be accessed through the external debug interface: