TRCEVENTCTL1R

External register TRCEVENTCTL1R bits [31:0] are architecturally mapped to AArch64 System register TRCEVENTCTL1R[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCEVENTCTL1R are RES0.

Attributes

Field descriptions

Bits [31:14]

OE, bit [13]
When TRCIDR5.OE == 1:

ETE Trace Output Enable control.

OE	Meaning
0b0	Trace output to any IMPLEMENTATION DEFINED trace output interface is disabled.
0b1	Trace output to any IMPLEMENTATION DEFINED trace output interface is enabled.

The reset behavior of this field is:

On a Trace unit reset, this field resets to 0.

Otherwise:

LPOVERRIDE, bit [12]
When TRCIDR5.LPOVERRIDE == 1:

Low-power Override Mode select.

LPOVERRIDE	Meaning
0b0	Trace unit Low-power Override Mode is not enabled. That is, the trace unit is permitted to enter low-power state.
0b1	Trace unit Low-power Override Mode is enabled. That is, entry to a low-power state does not affect the trace unit resources or trace generation.

Otherwise:

ATB, bit [11]
When TRCIDR5.ATBTRIG == 1:

AMBA Trace Bus (ATB) trigger enable.

If a CoreSight ATB interface is implemented then when ETEEvent 0 occurs the trace unit sets:

ATID == 0x7D.
ATDATA to the value of TRCTRACEIDR.

If the width of ATDATA is greater than the width of TRCTRACEIDR.TRACEID then the trace unit zeros the upper ATDATA bits.

If ETEEvent 0 is programmed to occur based on program execution, such as an Address Comparator, the ATB trigger might not be inserted into the ATB stream at the same time as any trace generated by that program execution is output by the trace unit. Typically, the generated trace might be buffered in a trace unit which means that the ATB trigger would be output before the associated trace is output.

If ETEEvent 0 is asserted multiple times in close succession, the trace unit is required to generate an ATB trigger for the first assertion, but might ignore one or more of the subsequent assertions. Arm recommends that the window in which ETEEvent 0 is ignored is limited only by the time taken to output an ATB trigger.

ATB	Meaning
0b0	ATB trigger is disabled.
0b1	ATB trigger is enabled.

Otherwise:

Bits [10:4]

INSTEN[<m>], bit [m], for m = 3 to 0

Event element control.

INSTEN[<m>]	Meaning
0b0	The trace unit does not generate an Event element <m>.
0b1	The trace unit generates an Event element <m> when ETEEvent <m> occurs.

Accessing this field has the following behavior:

When TRCIDR4.NUMRSPAIR == 0b0000, access to this field is RES0 .
Access is RES0 if TRCIDR4.NUMRSPAIR != 0b0000 and m > UInt(TRCIDR0.NUMEVENT).
Otherwise, access to this field is RW.

Accessing TRCEVENTCTL1R

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCEVENTCTL1R can be accessed through the external debug interface:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																		OE	LPOVERRIDE	ATB	RES0							INSTEN[3]	INSTEN[2]	INSTEN[1]	INSTEN[0]

TRCEVENTCTL1R, Trace Event Control 1 Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:14]

OE, bit [13]
When TRCIDR5.OE == 1:

Otherwise:

LPOVERRIDE, bit [12]
When TRCIDR5.LPOVERRIDE == 1:

Otherwise:

ATB, bit [11]
When TRCIDR5.ATBTRIG == 1:

Otherwise:

Bits [10:4]

INSTEN[<m>], bit [m], for m = 3 to 0

Accessing TRCEVENTCTL1R

TRCEVENTCTL1R can be accessed through the external debug interface:

TRCEVENTCTL1R, Trace Event Control 1 Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:14]

OE, bit [13]When TRCIDR5.OE == 1:

Otherwise:

LPOVERRIDE, bit [12]When TRCIDR5.LPOVERRIDE == 1:

Otherwise:

ATB, bit [11]When TRCIDR5.ATBTRIG == 1:

Otherwise:

Bits [10:4]

INSTEN[<m>], bit [m], for m = 3 to 0

Accessing TRCEVENTCTL1R

TRCEVENTCTL1R can be accessed through the external debug interface:

OE, bit [13]
When TRCIDR5.OE == 1:

LPOVERRIDE, bit [12]
When TRCIDR5.LPOVERRIDE == 1:

ATB, bit [11]
When TRCIDR5.ATBTRIG == 1: