TRCLSR, Trace Lock Status Register

The TRCLSR characteristics are:

Purpose

Indicates whether the Software Lock is implemented, and the current status of the Software Lock.

For additional information, see the CoreSight Architecture Specification.

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCLSR are RES0.

TRCLSR is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																													nTT	SLK	SLI

Reserved, RES0.

Software lock size.

Reads as 0b0.

Access to this field is RO.

The current Software Lock status.

SLK	Meaning
0b0	Software Lock is unlocked.
0b1	Software Lock is locked. Writes to the other registers in this component, except for the TRCLAR, are ignored.

This field reads as 0.

Indicates whether the Software Lock is implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SLI	Meaning
0b0	Software Lock is not implemented. Writes to the TRCLAR are ignored.
0b1	Software Lock is implemented.

This field reads as 0.

Access to this field is RO.

External debugger accesses to this register are unaffected by the OS Lock.

Component	Offset	Instance
ETE	0xFB4	TRCLSR

This interface is accessible as follows:

When !IsTraceCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6