The TRCSSCSR<n> characteristics are:
Returns the status of the corresponding Single-shot Comparator Control.
External register TRCSSCSR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCSSCSR<n>[31:0].
This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented and UInt(TRCIDR4.NUMSSCC) > n. Otherwise, direct accesses to TRCSSCSR<n> are RES0.
TRCSSCSR<n> is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STATUS | PENDING | RES0 | PC | DV | DA | INST | |||||||||||||||||||||||||
Single-shot Comparator Control status. Indicates if any of the comparators selected by this Single-shot Comparator control have matched. The selected comparators are defined by TRCSSCCR<n>.ARC, TRCSSCCR<n>.SAC, and TRCSSPCICR<n>.PC.
| STATUS | Meaning |
|---|---|
| 0b0 |
No match has occurred. When the first match occurs, this field takes a value of 1. It remains at 1 until explicitly modified by a write to this register. |
| 0b1 | One or more matches has occurred. If TRCSSCCR<n>.RST == 0 then:
|
The reset behavior of this field is:
Single-shot pending status. The Single-shot Comparator Control fired while the resources were in the Paused state.
| PENDING | Meaning |
|---|---|
| 0b0 |
No match has occurred. |
| 0b1 |
One or more matches has occurred. |
The reset behavior of this field is:
Reserved, RES0.
PE Comparator Input support. Indicates if the Single-shot Comparator Control supports PE Comparator Inputs.
| PC | Meaning |
|---|---|
| 0b0 |
This Single-shot Comparator Control does not support PE Comparator Inputs. Selecting any PE Comparator Inputs using the associated TRCSSPCICR<n> results in CONSTRAINED UNPREDICTABLE behavior of the Single-shot Comparator Control resource. The Single-shot Comparator Control might match unexpectedly or might not match. |
| 0b1 |
This Single-shot Comparator Control supports PE Comparator Inputs. |
Access to this field is RO.
Data value comparator support. Data value comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.
| DV | Meaning |
|---|---|
| 0b0 |
This Single-shot Comparator Control does not support data value comparisons. |
| 0b1 |
This Single-shot Comparator Control supports data value comparisons. |
This field reads as 0.
Access to this field is RO.
Data Address Comparator support. Data address comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.
| DA | Meaning |
|---|---|
| 0b0 |
This Single-shot Comparator Control does not support data address comparisons. |
| 0b1 |
This Single-shot Comparator Control supports data address comparisons. |
This field reads as 0.
Access to this field is RO.
Instruction Address Comparator support. Indicates if the Single-shot Comparator Control supports instruction address comparisons.
| INST | Meaning |
|---|---|
| 0b0 |
This Single-shot Comparator Control does not support instruction address comparisons. |
| 0b1 |
This Single-shot Comparator Control supports instruction address comparisons. |
This field reads as 1.
Access to this field is RO.
Must be programmed if TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0x2A0 + (4 * n) | TRCSSCSR<n> |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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