PMCNTEN

Enables the Cycle Count Register, PMCCNTR_EL0, and any implemented event counters PMEVCNTR<n>.

Configuration

External register PMCNTEN bits [63:0] are architecturally mapped to AArch64 System register PMCNTENSET_EL0[63:0].

External register PMCNTEN bits [63:0] are architecturally mapped to AArch64 System register PMCNTENCLR_EL0[63:0].

External register PMCNTEN bits [31:0] are architecturally mapped to AArch32 System register PMCNTENSET[31:0].

External register PMCNTEN bits [31:0] are architecturally mapped to AArch32 System register PMCNTENCLR[31:0].

This register is present only when FEAT_PMUv3_EXT64 is implemented. Otherwise, direct accesses to PMCNTEN are RES0.

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

PMICNTR_EL0 counter enable. Enables the instruction counter.

F0	Meaning
0b0	PMICNTR_EL0 disabled.
0b1	PMICNTR_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

C, bit [31]

PMCCNTR_EL0 enable. Enables the cycle counter register. Possible values are:

C	Meaning
0b0	PMCCNTR_EL0 is disabled.
0b1	PMCCNTR_EL0 enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

P<n>, bit [n], for n = 30 to 0

Event counter enable for PMEVCNTR<n>_EL0.

If PMCFGR.N is less than 31, bits [30:PMCFGR.N] are RAZ/WI.

P<n>	Meaning
0b0	PMEVCNTR<n>_EL0 is disabled.
0b1	PMEVCNTR<n>_EL0 is enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMCNTEN

Accesses to this register use the following encodings:

Accessible at offset 0xC10 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
Otherwise, accesses to this register are RW.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															F0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMCNTEN, Performance Monitors Count Enable register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<n>, bit [n], for n = 30 to 0

Accessing PMCNTEN

PMCNTEN, Performance Monitors Count Enable register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<n>, bit [n], for n = 30 to 0

Accessing PMCNTEN

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented: