PMEVFILT2R<n>

Purpose

Provides additional IMPLEMENTATION DEFINED configuration controls for PMU counters.

Each PMEVFILT2R<n> register can provide additional configuration controls for a PMU counter, where:

For values of n less than 31, if event counter n is implemented, then the controls are for PMU event counter <n>.

For n equal to 31, the controls are for the cycle counter, PMCCNTR_EL0;

For n equal to 32, if FEAT_PMUv3_ICNTR is implemented, the controls are for the instruction counter, PMICNTR_EL0;

For all other values of n, PMEVFILT2R<n> is not implemented.

Although this mapping is recommended, it is not required and the function of each register is IMPLEMENTATION DEFINED.

Configuration

This register is present only when FEAT_PMUv3_EXT is implemented and an implementation implements PMEVFILT2R<n>. Otherwise, direct accesses to PMEVFILT2R<n> are RES0.

Attributes

Field descriptions

When FEAT_PMUv3_EXT64 is implemented:

IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

Otherwise:

IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

Accessing PMEVFILT2R<n>

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT32 is implemented

[31:0] Accessible at offset 0x800 + (4 * n) from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

When FEAT_PMUv3_EXT64 is implemented

[63:0] Accessible at offset 0x800 + (8 * n) from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
Otherwise, accesses to this register are RW.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED

PMEVFILT2R<n>, Performance Monitors Event Filter Registers, n = 0 - 63