DBGVCR

AArch32 System register DBGVCR bits [31:0] are architecturally mapped to AArch64 System register DBGVCR32_EL2[31:0].

This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to DBGVCR are UNDEFINED.

Attributes

Field descriptions

When EL3 is implemented and EL3 is using AArch32:

NSF, bit [31]

NSI, bit [30]

Bit [29]

NSD, bit [28]

NSP, bit [27]

NSS, bit [26]

NSU, bit [25]

Bits [24:16]

MF, bit [15]

MI, bit [14]

Bit [13]

MD, bit [12]

MP, bit [11]

MS, bit [10]

Bits [9:8]

SF, bit [7]

SI, bit [6]

Bit [5]

SD, bit [4]

SP, bit [3]

SS, bit [2]

SU, bit [1]

Bit [0]

When EL3 is implemented and EL3 is using AArch64:

NSF, bit [31]

NSI, bit [30]

Bit [29]

NSD, bit [28]

NSP, bit [27]

NSS, bit [26]

NSU, bit [25]

Bits [24:8]

SF, bit [7]

SI, bit [6]

Bit [5]

SD, bit [4]

SP, bit [3]

SS, bit [2]

SU, bit [1]

Bit [0]

When EL3 is not implemented:

Bits [31:8]

F, bit [7]

I, bit [6]

Bit [5]

D, bit [4]

P, bit [3]

S, bit [2]

U, bit [1]

Bit [0]

Accessing DBGVCR

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1110	0b000	0b0000	0b0111	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGVCR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGVCR; elsif PSTATE.EL == EL3 then R[t] = DBGVCR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1110	0b000	0b0000	0b0111	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGVCR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGVCR = R[t]; elsif PSTATE.EL == EL3 then DBGVCR = R[t];

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NSF	NSI	RES0	NSD	NSP	NSS	NSU	RES0									MF	MI	RES0	MD	MP	MS	RES0		SF	SI	RES0	SD	SP	SS	SU	RES0

DBGVCR, Debug Vector Catch Register

Purpose

Configuration

Attributes

Field descriptions

When EL3 is implemented and EL3 is using AArch32:

NSF, bit [31]

NSI, bit [30]

Bit [29]

NSD, bit [28]

NSP, bit [27]

NSS, bit [26]

NSU, bit [25]

Bits [24:16]

MF, bit [15]

MI, bit [14]

Bit [13]

MD, bit [12]

MP, bit [11]

MS, bit [10]

Bits [9:8]

SF, bit [7]

SI, bit [6]

Bit [5]

SD, bit [4]

SP, bit [3]

SS, bit [2]

SU, bit [1]

Bit [0]

When EL3 is implemented and EL3 is using AArch64:

NSF, bit [31]

NSI, bit [30]

Bit [29]

NSD, bit [28]

NSP, bit [27]

NSS, bit [26]

NSU, bit [25]

Bits [24:8]

SF, bit [7]

SI, bit [6]

Bit [5]

SD, bit [4]

SP, bit [3]

SS, bit [2]

SU, bit [1]

Bit [0]

When EL3 is not implemented:

Bits [31:8]

F, bit [7]

I, bit [6]

Bit [5]

D, bit [4]

P, bit [3]

S, bit [2]

U, bit [1]

Bit [0]

Accessing DBGVCR

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}